Universally Testable AND-EXOR Networks

1. Universally Testable AND-EXOR Networks Ugur Kalay, Marek Perkowski, Douglas Hall Speaker: Alan Mishchenko Portland State University

2. Agenda • Introduction • desired properties of a test set • testing AND and EXOR gates • test scheme proposed by Reddy • Testing Two-level AND-EXOR Networks • implementation of the new testing scheme • experimental results • Testing Multi-Level AND-EXOR Networks • extending the scheme for multi-level circuits • Conclusions and Directions of Future Research

3. Introduction Requirements for a Test Set • 100% Fault Coverage • no fault simulation • Minimal (as few tests as possible) • shorter testing time • Universal (does not depend on the circuit) • portability of the pattern generator • reduced engineering • Regular (test patterns have certain structure) • simpler pattern generator • Good Scalability • easy pattern generator expandability

4. Introduction Testing AND gate 1 a 4 2 b 3 c

5. Introduction Testing EXOR gate a g b

6. Introduction • Reddy’s Positive Polarity Reed-Muller Testing Scheme Example: f = x1x2 Å x1x3Å x1x2x3 x0 x1 x2 x3 x0 x1 x2 x3 0 0 0 0 - 0 1 1 T1= 0 1 1 1 T2= - 1 0 1 1 0 0 0 - 1 1 0 1 1 1 1 -: don’t care * 100% Single Stuck-at Fault Coverage * Minimal (C = n + 4) * Universal * Regular Patterns * Linear increase * Large expression leads to long EXOR cascade

7. Introduction • Other Reed-Muller Canonical Forms PPRM (Positive Polarity Reed-Muller) x1x2x3 Å x1x2 FPRM (Fixed Polarity Reed-Muller) x1x2x’3 Å x2x’3 GRM (Generalized Reed-Muller) x1 Å x2 Å x’2x’3 • Free Expression ESOP(EXOR-Sum-of-Products) x1x2x3 Å x’1x’2x’3 ESOP GRM FPRM PPRM

8. Introduction • Comparison of the Number of Product Terms:

9. Testing Two-level AND-EXOR Networks * 100% single stuck at faults * Minimal C = n + 6 * Universal * Regular * Linear size increase * Perfect for BIST !

10. Testing Two-level AND-EXOR Networks Advantages of deterministic testing for ESOP • much shorter test cycle than pseudo-random and pseudo-exhaustive test sets • better fault coverage than a pseudo-random test set • no test point insertion required • a fixed, simple, and easily expandable pattern generator

11. Testing Two-level AND-EXOR Networks ESOP Deterministic Pattern Generator • Built-in Self-Test Circuitry for ESOP Networks PRPG EDPG Easily Testable 2-level ESOP Network Circuit Under Test MISR

12. Testing Two-level AND-EXOR Networks • ESOP Deterministic Pattern Generator • Linearly expandable • No initialization seed & circuitry • Much shorter cycle than a PRPG • Comparable size to PRPG (see later)

13. Testing Two-level AND-EXOR Networks • FSM (Part II) for EDPG

14. Testing Two-level AND-EXOR Networks Experimental Results • Comparisons of the number of test vectors for 100% single stuck-at fault fault coverage

15. Testing Two-level AND-EXOR Networks • Comparisons of the number of test vectors for 100% single stuck-at fault fault coverage (cont…)

16. Testing Two-level AND-EXOR Networks • Area and delay comparisons (LSI Logic Corp., 0.5 micron)

17. Testing Two-level AND-EXOR Networks • Area comparisons (Cont...)

18. Testing Two-level AND-EXOR Networks • Multiple Fault Simulation Results

19. Testing Multi-level AND-EXOR Networks • Two-level implementations • easily testable • large delay • It is possible to factorize the two-level ESOP expression • Universal testing of two-level ESOPs can be adopted for multi-level testing • requires scan registers

20. Testing Multi-level AND-EXOR Networks Example: The multi-output function, X = acefg Å ace’f’g’ Å ad’efgÅ ad’e’f’g’ Å ajh’i Å ajdÅ b’cefg Å b’ce’f’g’ Å b’d’efg Å b’d’e’f’g’Å b’h’ij Å bdj Y = bg’ Å a’cefg Å a’d’efg Z = adj Å b’dj Å ah’ijÅ b’h’ij can be factorized as, X = U[V(efg Å e’f’g’) Å jW] Y = bg’ Å a’efgV Z = jUW where, U = a Å b’ V = c Å d’ W = h’i Å d

21. Testing Multi-level AND-EXOR Networks • Implementation without testability improvements

22. Testing Multi-level AND-EXOR Networks • Inserting Literal Part

23. Testing Multi-level AND-EXOR Networks • Inserting Check Part

24. Testing Multi-level AND-EXOR Networks • Creating cascade of EXOR gates at each level

25. Testing Multi-level AND-EXOR Networks • Identifying ESOP Planes

26. Testing Multi-level AND-EXOR Networks • Inserting specialized Scan Registers and Scan Path

27. Testing Two-level AND-EXOR Networks TESTING SCHEME: • Each level is tested separately (can be improved) • ESOP planes of the same level are tested in parallel • Test vectors of the first level are applied from the primary inputs in parallel • Test vectors of the internal levels are applied from the primary inputs and from the scan registers • The bits applied from the scan registers are shifted into the scan path before applied in parallel • The network results are collected by the scan registers and shifted out, and/or observed from the primary outputs

28. Testing Multi-level AND-EXOR Networks • Implementation of Scan Registers • In normal circuit operation, only one mux delay added • Inserted only at the output of internal ESOP planes

29. Testing Multi-level AND-EXOR Networks • Scan Register mode of operations

30. Testing Multi-level AND-EXOR Networks • Scan Register mode of operations

31. Testing Multi-level AND-EXOR Networks • Scan Register mode of operations

32. Testing Multi-level AND-EXOR Networks • Critical Path Delay = 2.95 ns vs. 4.33 ns of 2-level impl.

33. Testing Multi-level AND-EXOR Networks • (4 AND3 + 5 AND2 + 24 EXOR2) gates + 5 SR vs. (17 AND3 + 24 AND2 + 33 EXOR2) gates of 2-level impl.

34. Future Directions • Developing a universal test set for bridging and stuck-open faults • Developing a factorization/decomposition method targeting EXOR-based multi-level synthesis and universal (deterministic) testability

35. Advantages and Disadvantages of the New Scheme • Test set is exponentially smaller than a pseudorandom test set and much smaller than algorithmically generated test set for 100% coverage of single stuck-at faults • Properties of deterministic pattern generator for BIST • easy to implement (small area overhead) • does not require seed generation • guarantees 100% testability • Detects significant fraction of multiple stuck-at faults and bridging faults • Cascade of EXOR gates is relatively slow • Area of the AND-EXOR circuit is relatively large • ESOP factorization algorithm is computationally complex

36. Rereferences [1] Ugur Kalay, Douglas V. Hall, Marek A. Perkowski. “A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits”. IEEE Trans. Comp. Vol. 49, N3, March 1999, pp.267-276.[2] Ugur Kalay, Marek Perkowski. “Rectangle Covering Factorization of EXORs into Scan-Based Levelized Circuits with Universal Test Set”. Proc. of International Workshop on Application of Reed-Muller Expansion in Circuit Design. 1999.