1 / 58

OPTIMAL ELECTRONIC CIRCUITS and MICROSYSTEMS NETWORKED DESIGNER

NTUU "KPI" 1898. OPTIMAL ELECTRONIC CIRCUITS and MICROSYSTEMS NETWORKED DESIGNER. Prof. ANATOLY PETRENKO National Technical University of Ukraine “Kiev Polytechnic Institute”, Tel./FAX +380 44 280 90 46, e-mail: petrenko@cad.kiev.ua.

verity
Download Presentation

OPTIMAL ELECTRONIC CIRCUITS and MICROSYSTEMS NETWORKED DESIGNER

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. NTUU "KPI" 1898 OPTIMAL ELECTRONIC CIRCUITS and MICROSYSTEMS NETWORKED DESIGNER Prof. ANATOLY PETRENKO National Technical University of Ukraine “Kiev Polytechnic Institute”, Tel./FAX +380 44 280 90 46, e-mail: petrenko@cad.kiev.ua

  2. Outline • Networked CAD tools • International co-operation Experience • ALLTED – All Technology Designer • Novel numerical methods • Results of solving the benchmark circuits • Optimization example • AND Logical Circuit on OET • Possible co-operation SW, EB, Grid

  3. Networked CAD tools • Remote access to CAD tools and collectively execution the joint Projects; • Meeting different requirements to hardware of a server and a client ; • New level of functional cooperation via GRID infrastructure; • Possibilities for Small and Middle enterprises to take a part in international work force distribution developing competitive products. SW, EB, Grid

  4. ALLTED – All Technology Designer Previous versions of this system (named SPARS, PRAM-01, PRAM-PK, PRANS for EC and SM computers) were used in the former Soviet Union as the branch Ministry of the Defense industry standard OST V3-4776-80 for circuit design automation and similar standards for the Ministries of General and Average Machinobuilding and Radio industry. ALLTED is especially useful in the development of new products which combine various physical phenomena in one device SW, EB, Grid

  5. International co-operation Experience • Digital (Alpha Processor simulation) • Intel (Parallel computation, Formal verification, Layout extraction, VLSI Interconnects Model-Order Reduction ,ALOE to Cadence / Cadence toALOEconverters) • General Electric (MEMS Model design) • Motorola( Signal Processors implementation) • Sun ( Layout verification) • Panasonic (Remote Access to Networked Appliances ) • Melexes (VLSI design with 0.25 u) • HPC –Germany ( RF circuits design) • EC Projects( Tempus, Inco- Copernicus) • STCU Projects( Remote Simulation, MEMS Design) SW, EB, Grid

  6. Layout visualization SW, EB, Grid

  7. PostGL-3D Open GL Viewer SW, EB, Grid

  8. ALLTED – All Technology Designer • ALLTEDis an acronym forALLTEchnologyDesigner. It was developed not only for simulation and analysis, but for processing project procedures such as: • parametric optimization tasks; • optimal tolerance assignments; • centering availability regions; • yield maximization; • design of Nonlinear Dynamic Systems composed of either/and electronic, hydraulic, pneumatic, mechanical, electromagnetic, and other elements. SW, EB, Grid

  9. ALLTED – All Technology Designer SW, EB, Grid

  10. ALLTED – Shematic editor SW, EB, Grid

  11. ALLTED in distributed Web environment SW, EB, Grid

  12. ALLTED usage examples SW, EB, Grid

  13. ALLTED usage examples SW, EB, Grid

  14. ALLTED usage examples SW, EB, Grid

  15. ALLTED usage examples SW, EB, Grid

  16. ALLTED usage examples SW, EB, Grid

  17. ALLTED usage examples SW, EB, Grid

  18. System on a Chip SW, EB, Grid

  19. System on a Chip SW, EB, Grid

  20. ALLTED offers: • Faster simulation speed and improved numerical convergence; • Sensitivity analysis for frequency and transient analyses; • Comprehensive optimization procedure and optimal tolerances assignment ; • Alternative approach to the secondary response parameters determination (delays, rise and fall times, etc.); • Powerful user-defined modeling capability. • Original way of generating a system-level model of MEMS from FEM component equations. SW, EB, Grid

  21. Novel numerical methods • The new solution curve-search method for Steady State (DC) Analysis which provides the quick descent to the solution point region from any starting point • The Diagonal Modification Method which helps considerably preserve convergence of linearized equations solution without re-ordering when matrix element values change from one iteration to another iteration . • The Optimization Variable-order Methods which is equivalent to taking into consideration five terms of Tailor’s series for the Goal functionwhich considerably improve determination of a direction to the optimal point SW, EB, Grid

  22. Novel numerical methods • The Implicit Linear Multi-step Variable-order Integration Method for Transient Analysis(TR) which uses high order back differences that allows to select the proper one resulting in minimization of solution time for prescribed accuracy. • The Optimal Tolerances Assignment Method which is based on applying Optimization procedures and takes into account the prescribed deviations of Controlled Output Parameters • Statistical Yield Maximization Method which provides “centering” the solution point in the region of acceptable solutions SW, EB, Grid

  23. DC Method Example 1 SW, EB, Grid

  24. Diagonal modification method SW, EB, Grid

  25. TR solution approach SW, EB, Grid

  26. Optimization Variable order method SW, EB, Grid

  27. INTEL AWARD Конкурс исследовательскихпроектов области автоматизации Проектирования интегральных схем награждается ПЕТРЕНКО АНАТОЛИЙ ИВАНОВИЧ Национальный Технический Университет Украины «Киевский политехнический институт ПРОЕКТ Разработка эффективных численных методов моделирования и оптимизации схемотехнических решений для СБИС SW, EB, Grid

  28. Results of solving the benchmark circuits of the Microelectronics Center in North Carolina Circuit ALLTEDPSPICEGain Iteration Iteration INPUT358 755 2.11 CHARGE4682 7625 1.63 FADD32 873 2280 2.61 SW, EB, Grid

  29. CHARGE Circuit with BISIM 49 Models SW, EB, Grid

  30. ALLTED and PSPICE v.9.2 outputs: SW, EB, Grid

  31. FADD32 Circuit (288 transistors) SW, EB, Grid

  32. ALLTED and PSPICE v.9.2 outputs SW, EB, Grid

  33. Simulation results obtained by ALLTED and HSPICE SW, EB, Grid

  34. MIKE2 Circuit with bsim13 models: SW, EB, Grid

  35. ALLTED and HSPICE outputs for Mike2_bisim13: SW, EB, Grid

  36. ALLTED statistics of the transient analysis of Mike 2 • S t a t i s t i c s • Number of steps = 256 • Number of iterations = 528 • Number of steps per order: • order - 0 - = 26 • order - 1 - = 46 • order - 2 - = 90 • order - 3 - = 71 • order - 4 - = 19 • order - 5 - = 4 • order - 6 - = 0 • Number of rejected steps = 23 • HSPICE uses only 2-d order integration formula SW, EB, Grid

  37. Optimization example 1 Circuit: Operational Amplifier RCA 3040 with 11 transistors Task: calculate the resistances R1, R3 and R4 values in such a way, that the output impulse amplitude on resistor R11 would be equal to 8 V. 0.1       <=        R1       <=        10 0.1K    <=        R3       <=         10 0.1K    <=        R4       <=         10K SW, EB, Grid

  38. Task file: tr; optim; const DCERR=1.e-6; const tmax=90, MINSTEP=1e-4, ERR=0.01, LERR=0.1, REVAL=3; # TR OUTPUT parameters fix T3=MINF(UR11); fix T4=MAXF(UR11); INT DURF=T4-T3; const method=120; varpar R1(0.01,10), R3(1,100), R4(1,100); of DIF1 = F1(8/DURF); plot Ur11; Objective function DIF1 = .3146487870E-07 R E S U L T S O F O P T I M I Z A T I O N Variable parameters R1 = .1000000000E+01 R3 = .6778549874E+01 R4 = .6778549874E+01 Directive F I X output characteristics T3 = 2.47580528 T4 = 10.4756279 Directive I N T output characteristics DURF = 7.99982262 Optimization example 1 SW, EB, Grid

  39. Optimization example 2 Circuit: Active RC filter RAD • Task; • dc; • ac; • optim; • const lfreq=0.0025, ufreq=0.005,METHOD=152; • TF K1=V6/UE1; • plot MA.K1; • fix f1=MAXA(MA.K1); • fix f2=MAXF(MA.K1) • func f5=F7(1/f2); • of error=f5(1/f5); • varpar Alpha.OP1(3E1,4E3), Alpha.OP2(0.6E1,1E3); • limit Lim2=F2(0.003734/f1); Constraints RESULTS OF OPTIMIZATION ERROR = 0.1786038652D-01 Variable parameters ALPHA.OP1 = 0.3709765013D+04 ALPHA.OP2= 0.1000000000D+04 SW, EB, Grid

  40. Interactive Tasks formation SW, EB, Grid

  41. Optimal tolerance assignment example: Circuit: Operational AmplifierRCA 3040 with 11 transistors Task: calculate the resistances R2, R3 and voltage source E2 tolerances values for which the output minimal voltage UR11 changes +/- 5% of itsvalue. task; dc; tr; tolas; const tmax=90 ,ERR=0.01, LERR=0.1, REVAL=3; FIX UM=minf(UR11); const TOLERR=0.001; control UM(5,5); varpar E2(10),R2,R3(10); O P T I M A L T O L E R A N C E S *********************************** Parameter Nominal Tolerance value % abs E2 .1200000000E+02 +- 19.682 +- -.2361829758E+01 R2 .1000000015E+00 +- 4.614 +- .4613934550E-02 R3 .1000000000E+01 +- 3.697 +- .3696829081E-01 SW, EB, Grid

  42. Mixed Analyses example Macromodel 2-input AND Cell(0,1,2,3); j1(1,0)=f300(ut,rbx/uj1); j2(2,0)=f300(ut,rbx/uj2); e1(3,0)=f310(u1,u0,f1,d1,f0,d0,r1,r0,-1/ue1,ie1); list m1.icand; rbx=50; ut=1; u0=0.3; u1=2.4; f1=-1; d1=10; f0=-1; d0=10; r1=0.1; r0=0.02; Now we are going to provide possibilities for users to access NetALLTED resources through the Internet for optimal Microsystems design. SW, EB, Grid

  43. The example of Micro-machined Ultrasonic Transducer simulation SW, EB, Grid

  44. AND Logical Circuit on OET One-electron transistor model SW, EB, Grid

  45. L W T Er H Microwave Devices in ALLTED • Model of transmission linewith a negative inductance Fig. 8 The SW, EB, Grid

  46. ALLTED adaptation to a new application • New components mathematical models incorporating ( in equations form) • New graphical symbols for components, if any • New sections in library with components parameters • OF, LIMIT and FUNC libraries upgrading if any • Numerical procedures constants adjusting for new types of tasks SW, EB, Grid

  47. MEMS Simulation level System level Circuit level Components level SW, EB, Grid

  48. Model Order reduction (Krylov- Arnoldi Method)

  49. Circuit model reduction method SW, EB, Grid

  50. Y/∆ transformation SW, EB, Grid

More Related