Using Virtual Platform for the development and verification of embedded software

1. Using Virtual Platform for the development and verification of embedded software April 14, 2013 Sandeep Jain, Rajesh Jain Digital Networking, Freescale Veller Yossi Mentor Graphics Updated Apr 2013

2. Outline • Virtual Platforms – Challenges & Requirements • Freescale QorIQ T4240 Overview • Using VP for Software bring-up • Software Power Tradeoff Analysis • Board Level Simulation • Conclusion • References

3. Virtual Platforms – Challenges & Requirements • Embedded Software Development Challenges • Developing, integrating, validating and optimizing software in the context of target hardware, before the hardware is available • SoCs are becoming more and more complex • Multiple heterogeneous cores, hardware accelerators, peripherals, complex memory hierarchy with hardware supported coherency • SoC level simulation is not sufficient and board level Virtual Platform is a must • Virtual Platforms Requirements • Fast, accurate and low cost • Debug capabilities • Power/performance trade-off analysis • Mentor T4240 Virtual Platform jointly developed by Freescale and Mentor Graphics to meet these goals

4. Freescale QorIQ T4240 Communications Processor • * http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=T4240

5. Freescale QorIQ T4240 VP Overview • Developed using Freescale internal C++ modeling framework • Comprises of models/libraries developed over several years • Fast DBT core models with simulation performance of 100+ MIPS • Models for various hardware accelerators, IO peripherals and memory controllers • Models verified using the same workloads which are used for RTL verification • Integration with Freescale CW IDE, python based CLI, etc

7. Introducing Vista™ • Vista is an IDE that enables • Scalable SC/TLM Modeling • Timing / Power layers • Quickly assemble, configure and validate the SoC • Profile & Analyze SoC attributes: cache hit/miss, latencies, payload throughputs • Integrate Drivers, Operating System and Applications Embedded System Bringup Virtual “Target” Device GPU LCD Video MPEG CPU Vista Architect Modeling Debug Analysis Embedded SW Device Power / Timing UI™ Bridge USB ETHERNET PCI EXPRESS SDRAM DMA TLM Platform Application Stacks Peripherals Middleware, Agents Android™ Linux® Others® UART GPIO Timer PHY PHY PHY DDR3 Single Core Virtual Prototype Executable Dual Core

8. Freescale QorIQ T4240 VP Integration with Vista • Integrate into an open standard TLM framework • Access a to broad industry model catalog • Scalable with Timing/Power layer • T4240 Freescale VP integrated into Mentor Vista SystemC environment using existing APIs from Freescale C++ framework • T4240 SoC model is represented by a sc_thread • To enable co-operative multithreading, end-of-time-quanta callbacks cause the sc_thread to yield control to the SystemC kernel • The multithreaded Posix execution of the T4240 is synchronize with the single SystemCsimulation pthread

9. Using VP for software bring-up • Invoking the simulator

10. Using VP for software bring-up • Loading software images

11. Using VP for software bring-up • Accessing Registers and Memory

12. Using VP for software bring-up • Breakpoints and Watchpoints

13. Using VP for software bring-up • Logging and Tracing

14. Using VP for software bring-up • Events and callbacks

15. Linux Boot Demo on Freescale QorIQ T4240 VP

16. Freescale QorIQ T4240 Power Saving Modes • T4240 features software controlled power management • Minimizes power consumption of blocks when they are idle • Optimizing Software applications for low power consumption • Core doze, sleep, deep-sleep, off • Power gating to vector execution unit within cores • Cluster on and off • Device/peripheral power activity • Dynamic voltage/frequency scaling effects

17. Software Power Analysis: Concept T3 : Wakes Up T4 : Wakes Up T2 : Enters Low Power State (PH15) T1 : Enters Low Power State (PW20) C2 C 3 C 4 C1 Power Level Other Blocks Simulation Time CPU 3 add r0,r1,r2 load r4, addr … … CPU 1 add r0,r1,r2 load r4, addr … … CPU 2 add r0,r1,r2 load r4, addr … … CPU 4 add r0,r1,r2 load r4, addr … … T0 T1 T2 T3 T4 wait Update PCPH15SETR Update PCPH15CLR msgsnd

18. Mentor Vista Power Modeling • Adding power attributes based on functional states for each CPU • Optionally define communication power • Power simulation adaptive to clock and VDD scaling (VDFS) Vista Power Model Clock Tree Power Static Power Dynamic Power Clock Power States Computation Power Communication Power VDD

19. Mentor Vista Power Profile • The graph below visualized the power consumption of each of the 4 CPU’s during Linux boot

20. Mentor Vista Power Profile Demo

21. Board Level Simulation • Freescale non-systemC IO controller model (PCIe) is connected with Mentor SystemC IO device, Ethernet Controller model, using TLM-2.0 based methodology. • TLM2.0 LT Compliant layer is introduced between controller model and device model. • Controller signal level information is wrapped into one packet and the packet is sent as TLM extension along with TLM generic payload.

22. Board Level Simulation (contd..) Makes controller model Interoperable PCIe controller model (C++) TLM TLM PCIe device model (SystemC) PCIe Controller Model (using C++ internal framework) PCIe Device Model (using SystemC ) TLM2.0 LT APIs PCI set/get map base PCI set/get map size PCI set/get map enable PCI set/get map offset PCI data to/from memory

23. Mentor Vista PCIe connectivity • Verification & analysis of the PCIe channels traffic

24. Mentor Vista PCIe connectivity Demo

25. Conclusion • Successful Integration of Freescale T4240 model with Vista SystemC environment • Increased scope of VP from SoC level simulation to board level simulation • Added software level power tradeoff analysis capabilities • Achieved early software enablement • T4240 24-vCPU SMP Linux • T4240 Topaz Hypervisor • Several networking applications like IP Forwarding, IPSec Forwarding, etc

26. References

27. Thank You!