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FPGA Coprocessing in Multi-Core Architectures for High-Performance Embedded Computing Workshop

Unleash the potential of FPGA coprocessing in multi-core architectures for DSP applications. Explore algorithmic gains, ESL using PSP, RTL for FPGA, and Intel and AMD solutions. Learn how FPGA seamlessly integrates with the main loop and accelerates functions off-processor.

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FPGA Coprocessing in Multi-Core Architectures for High-Performance Embedded Computing Workshop

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  1. FPGA Coprocessing in Multi-Core Architectures for DSP High Performance Embedded Computing Workshop 18-20 September 2007 J Ryan Kenny Bryce Mackin Altera Corporation 101 Innovation Drive San Jose, CA 95134

  2. Algorithmic Gains with FPGA CoProcessing • Many Off-Processor Acceleration Functions have been benchmarked for FPGA CoProcessing • Acceleration Depends on Algorithm and Logic Division Process

  3. Example—Financial Solution (50x +) ESL: first step:PSP for ImpulseC C source code • Main loop Single and double-precision IEEE 754 floating-point arithmetic supported in FPGA (XDI Library) and automatically inferred from code • Compile C to HDL All components connected via Avalon™ fabric Impulse C module • Main loop SOPC Builder XDI local memory interface HyperTransport interface • Make script-driven calls to Altera tools Intel Module All RTL for FPGA complete Altera project files Intel: FSB at 1066 Mhz, ~ 8.5 GB/s AMD:16-Lane HT, 400Mhz DDR, 3.2 GB/s AMD Module

  4. Solution Examples (Xtreme Data Dual & Notional Quad Architecture) Intel Xeon • FPGA uses all motherboard resources meant for CPU: • HyperTransport Links, Memory interface, power supply, heat-sink • Usable in rack-mount or high-density, “blade” server systems, where PC boards don’t work AMD Opteron AMD Module via HyperTransport • Process is Scalable for Quad Processors • Cores Available to interface with AMD HyperTransport • High Bandwidth, Low Latency • Applications and Benchmarks Coming Soon! Intel Module connects via Front Side Bus

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