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Unit 5 Programmable Logic and Storage Devices – RAMs and FPGAs. Unit 5-1 Static Random Access Memory (SRAM). Reason for using random access memory (RAM) Computers and other digital systems perform operations that retrieve, manipulate, transform and store data
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Unit 5 Programmable Logic and Storage Devices –RAMs and FPGAs Department of Communication Engineering, NCTU
Unit 5-1 Static Random Access Memory (SRAM) Department of Communication Engineering, NCTU
Reason for using random access memory (RAM) • Computers and other digital systems perform operations that retrieve, manipulate, transform and store data • Read only memories (ROMs) can not dynamically store data • Registers support fast and random storage, but cannot be used for mass storage because they are implemented with FFs and occupy too much physical area • RAM is faster and occupies less area than a register file • Most RAMs are volatile- the information vanishes after power is removed from the device • There are two types of RAMs: static and dynamic • Dynamic RAMs need refresh and static RAMs don’t Department of Communication Engineering, NCTU
Word EN Bit_line Bit_line_N cell Cell_N Word EN Bit_line Bit_line_N • Basic static RAM (SRAM) structure Department of Communication Engineering, NCTU
CS data_out WE data_in • Level-sensitive Verilog models of RAMs • A 32K 8 SRAM module SRAM1 (data_out, data_in, CS_N,WE_N); output data_out; input data_in; input CS_N, WE_N; wire data_out= (CS_N==0) ? (WE_N==0) ? data_in : data_out : 1’bz; endmodule data_in Demux Demux Demux Demux Demux Demux Demux Demux D_IN D_IN D_IN D_IN D_IN D_IN D_IN D_IN Decoder CS CS CS CS CS CS CS CS WE WE WE WE WE WE WE WE OE OE OE OE OE OE OE OE D_OUT D_OUT D_OUT D_OUT D_OUT D_OUT D_OUT D_OUT Mux Mux Mux Mux Mux Mux Mux Mux data_out Department of Communication Engineering, NCTU
CS OE data WE • Basic static RAM (SRAM) structure • A 16K SRAM module SRAM2 (data, CS_N,WE_N,OE_N); output data_out; input CS_N, WE_N,OE_N; wire latch_out= ((CS_N==0) && (WE_N==0)&&(OE_N==1)) ? data : latch_out; assign data= ((CS_N==0) && (WE_N==1)&&(OE_N==0)) ? latch_out: 1’bz; endmodule A10 A9 A0 Column Input/Output A3 A2 A1 A0 D7 D6 D5 D4D3 D2 D1 D0 Department of Communication Engineering, NCTU
Unit 5-3 Altera FPGA Architecture Department of Communication Engineering, NCTU
Architecture of Stratix • Logic array blocks (LABs) : 10 logic elements (LEs) in each LAB • Memory block structures • 512 RAM: simple dual-port memory blocks (512 +parity =576) • M4K RAM: true dual-port memory blocks (4K + parity =4608) • M-RAM: true dual-port memory blocks (512K+parity=589,824) • DSP blocks • 9×9- or 18×18- or 36×36-bit multiplier with add and subtraction • 18-bit input shift registers • I/O element (IOE) : contains a bidirectional I/O buffer and six registers • Supports single-ended, differential I/O standards and external memory devices such as DDR-SDRAM Department of Communication Engineering, NCTU
Logic elements (LE) : the smallest unit of logics in the Stratix architecture each of which contains : • A four-input LUT • A programmable register : • can be configured for D, T, JK and SR FFs • Asynchronous data, • Support single bit addition and subtraction Department of Communication Engineering, NCTU
clk a A0 A1 A2 A3 d(A3)+ d d(A0)+ d(A1)+ d(A2)+ we d(A1) q d(A0) d(A2) • Single-Clock SRAM without read-through-write behavior module ram_infer (q, a, d, we, clk); output reg [7:0] q; input [7:0] d; input [6:0] a; input we, clk; reg [7:0] mem [127:0]; always @ (posedge clk) begin if (we) mem[a] <= d; q <= mem[a]; // q doesn't get d in this clock cycle end endmodule Department of Communication Engineering, NCTU
clk a A0 A1 A2 A3 d(A3)+ d d(A0)+ d(A1)+ d(A2)+ we d(A1)+ q d(A0)+ d(A2)+ • Single-Clock SRAM with read-through-write behavior module ram_infer (q, a, d, we, clk); output [7:0] q; input [7:0] d; input [6:0] a; input we, clk; reg [6:0] read_add; reg [7:0] mem [127:0]; always @ (posedge clk) begin if (we) mem[a] <= d; read_add <= a; end assign q = mem[read_add]; endmodule Department of Communication Engineering, NCTU
Unit 5-4 Model Simulation Library Department of Communication Engineering, NCTU
Choose a working directory that you want to store the compiled Libraries Department of Communication Engineering, NCTU
Create a new library for the compiled library Department of Communication Engineering, NCTU
Create the library named: stratix_atoms Repeat the above two procedures For the following two libraries altera_mf 220model Department of Communication Engineering, NCTU
Compile the stratix_atoms Library Department of Communication Engineering, NCTU
Choose the stratix_atoms.v file Department of Communication Engineering, NCTU
Notice the difference from Map the stratix_atoms to the compiled stratix_atoms library Department of Communication Engineering, NCTU
Unit 5-5 Simulation with Altera mega-functions Department of Communication Engineering, NCTU
Load Altera_mf library Department of Communication Engineering, NCTU
Load Altera_mf Then you are done Department of Communication Engineering, NCTU
Unit 5-5 Post Layout Simulation Department of Communication Engineering, NCTU
Specify options for Generating output files For modelsim File name : *.vo Department of Communication Engineering, NCTU
Import top-level Test bench and top-level design *.vo only Department of Communication Engineering, NCTU
Load Stratix_atoms library Department of Communication Engineering, NCTU
