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Lecture 13 PicoBlaze I/O & Interrupt Interface

Lecture 13 PicoBlaze I/O & Interrupt Interface. ECE 448 – FPGA and ASIC Design with VHDL. Required reading. P. Chu, FPGA Prototyping by VHDL Examples Chapter 16, PicoBlaze I/O Interface Chapter 17, PicoBlaze Interrupt Interface. Syntax and Terminology.

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Lecture 13 PicoBlaze I/O & Interrupt Interface

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  1. Lecture 13PicoBlaze I/O & Interrupt Interface ECE 448 – FPGA and ASIC Design with VHDL

  2. Required reading • P. Chu, FPGA Prototyping by VHDL Examples • Chapter 16, PicoBlaze I/O Interface • Chapter 17, PicoBlaze Interrupt Interface ECE 448 – FPGA and ASIC Design with VHDL

  3. Syntax and Terminology Syntax Example Definition sX KK PORT(KK) PORT((sX)) RAM(KK) Value at register 7 Value ab (in hex) Input value from port 2 Input value from the port specified by register s1 Value from the RAM location 4 s7 ab PORT(2) PORT((s1)) RAM(4)

  4. Addressing modes Immediate mode SUB s7, 07 ADDCY s2, 08 s7 – 07  s7 s2 + 08 + C  s2 Direct mode sa + sf  sa PORT(2a)  s5 ADD sa, sf INPUT s5, 2a Indirect mode s3 RAM((sa)) PORT((s2))  s9 STORE s3, (sa) INPUT s9, (s2)

  5. Output Decoding of Four Output Registers ECE 448 – FPGA and ASIC Design with VHDL

  6. Output Instructions C Z OUTPUT sX, KK PORT(KK) <= sX OUTPUT sX, (sY) PORT((sY)) <= sX − − DIR IND − −

  7. Timing Diagram of an Output Instruction ECE 448 – FPGA and ASIC Design with VHDL

  8. Truth Table of a Decoding Circuit ECE 448 – FPGA and ASIC Design with VHDL

  9. Input Instructions C Z INPUT sX, KK sX <= PORT(KK) INPUT sX, (sY) sX <= PORT((sY)) − − DIR IND − −

  10. Block Diagram of Four Continuous-Access Ports ECE 448 – FPGA and ASIC Design with VHDL

  11. Timing Diagram of an Input Instruction ECE 448 – FPGA and ASIC Design with VHDL

  12. Block Diagram of Four Single-Access Ports ECE 448 – FPGA and ASIC Design with VHDL

  13. FIFO Interface clk rst rst clk FIFO dout din 8 8 empty full write read ECE 448 – FPGA and ASIC Design with VHDL

  14. Operation of the First-Word Fall-Through FIFO ECE 448 – FPGA and ASIC Design with VHDL

  15. Operation of the “Standard” FIFO A B C D −−−−− ECE 448 – FPGA and ASIC Design with VHDL

  16. Interrupt Flow ECE 448 – FPGA and ASIC Design with VHDL

  17. Timing Diagram of an Interrupt Event ECE 448 – FPGA and ASIC Design with VHDL

  18. ECE 448 – FPGA and ASIC Design with VHDL

  19. Interrupt Related Instructions RETURNI ENABLE PC <= STACK[TOS] ; TOS <= TOS – 1; I <= 1; C<= PRESERVED C; Z<= PRESERVED Z RETURNI DISABLE PC <= STACK[TOS] ; TOS <= TOS – 1; I <= 0; C<= PRESERVED C; Z<= PRESERVED Z ENABLE INTERRUPT I <=1; DISABLE INTERRUPT I <=0;

  20. Interrupt Interface with a Single Event ECE 448 – FPGA and ASIC Design with VHDL

  21. Interrupt Interface with Two Requests ECE 448 – FPGA and ASIC Design with VHDL

  22. Time-Multiplexed Seven Segment Display ECE 448 – FPGA and ASIC Design with VHDL

  23. Block Diagram of the Hexadecimal Time-Multiplexing Circuit ECE 448 – FPGA and ASIC Design with VHDL

  24. Hexadecimal Multiplexing Circuit Based on PicoBlaze and mod-500 Counter ECE 448 – FPGA and ASIC Design with VHDL

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