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Y. Ermoline et al. Level-1 Calorimeter Trigger Joint Meeting, Heidelberg, January 11-13, 2010

Algorithms and TP. Y. Ermoline et al. Level-1 Calorimeter Trigger Joint Meeting, Heidelberg, January 11-13, 2010. Algorithm to implement. Exclusive hit multiplicities trigger: Use spatial overlap of em, tau and jets RoIs to identify overlaps

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Y. Ermoline et al. Level-1 Calorimeter Trigger Joint Meeting, Heidelberg, January 11-13, 2010

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  1. Algorithms and TP Y. Ermoline et al. Level-1 Calorimeter Trigger Joint Meeting, Heidelberg, January 11-13, 2010

  2. Algorithm to implement • Exclusive hit multiplicities trigger: • Use spatial overlap of em, tau and jets RoIs to identify overlaps • 0.2 x 0.2 em/tau RoI coordinate precision is sufficient • Test vectors for VHDL simulation from MC • Output of current L1Calo algorithm ignoring data transfer limitations • RoI maps with 0.2 x 0.2 precision from CPMs/JEMs • 32 (phi) x 32 (eta) = 1024 bins • x 16 bits for CP (em/tau thresholds) • x 8-bits for JP (jet thresholds) • Simple text files • 32 lines, first line for phi=0, last line for phi=31 • each line: 32 hex numbers, first for eta=0, last for eta=31 • Read into data arrays in VHDL testbench • New topology algorithm is applied on the test vectors both in MC and VHDL and results are compared.

  3. Realistic input data • 160 MHz (CPM/JEM -> CMM): 96 bits(24x4) + 1 line clock • JEM ROIs: 8 11-bit words (precision 0.2 x 0.2) - 88 bits (OK ) • 2 bits ROI position, 8 bits threshold + 1 status (saturation) • CPM ROIs: 16 8-bit words (precision 0.2 x 0.2) - 128 bits (notOK) • No 2 bits ROI fine position (0.1 x 0.1), no 2 status bits • Possible solution for CPM (to be proved by MC): • Define a limited number of "topological processing" thresholds and transfer only bit-maps for those thresholds • e.g. – 4 thresholds => 16 4-bit words (precision 0.2 x 0.2) - 64 bits • + 24 bits of inclusive hit multiplicities • CMM(CPM) to TP (Topological Processor) data transfer • CMM will receive data at 160 Mb/s from max 16 modules • 24 lines for the data/parity + clock • 384 bits @ 160 MHz => 61.44 GBit/s • 12 fibers ribbon optical link driven by 6.5 GBit/s GTX serial transceivers • Muon data from 16 MIOCTs (Muon Interface OCTant module) • 2 fibers / MIOCT

  4. em/tau jet Algorithm • Count inclusive hit multiplicities per jet threshold • Output: 8 3-bit counts (more bits?) • Overlap identification algorithm • which ROI maps overlaps to identify? • 4+4 possible overlaps per jet threshold • 8 enable bits – 1 enable-bit per em/tau threshold • jet window size 4 x 4 • Look for em/tau RoIsin 3 x 3 window around jet ROI • If em/tau RoIis found, set jet ROI overlap bit • Muon data? • Output: 8 JP overlap RoImaps - 8 overlap bits per bin • Count exclusive hit multiplicities per jet threshold • Output: 8 counts (same as in the current design)

  5. Few assumptions on TP development TP hardware will probably not be used in the Phase II but firmware (algorithms) may be used concentrate on algorithms MC study and implementation TP shall be developed relatively quickly to be used in Phase I minimize HW/SW design efforts (re)use existing knowledge, experience and “IP” parts TP will be deployed together with the current L1Calo infrastructure (re)use the existing HW (modules, crates, backplanes) & SW parts TP maybe commissioned and tested in parallel with the running L1Calo system may have implications for the developments of the new modules and may also require some backward compatible modifications of the current system, including data formats.

  6. Simplified TP system block-diagram Get data out of L1Calo trigger CMM++ / upgraded CMM Distribute L1Calo and muon data to multiple TP modules Multiple CMM outputs / GOLD Collect data processing results CP/JP crate backplane Send data to CTP at 80 MHz CMM++ / upgraded CMM CTPIN+ L1Calo legacy: CP/JP crate with backplane TCM, VME SBC, ROD+ L1Calo TP Muon CMM+ ROD+ CTP

  7. Upgraded CMM development scenarios CMM++ (fully new design) Replacement for existing merger modules Single, large FPGA collects, processes and distributes ROI data. Topological algorithms on CMM++ and/or new topological processor subsystem Ideas for staged upgrade path using CMM++ 2 year development time (components and manpower) CMM+ (min re-design, backward compatible) Provide all the necessary functionalities and interfaces to replace the current CMM Need old G-Link chips Be able to feed all the backplane data onwards to the topological processor New firmware in the Crate Merging Logic for incoming data serialization + SNAP12(s) on board Optionally: one large FPGA instead of two Faster development: RAL (CMM), Mainz (BLT/GOLD) and Stockholm (10Gb) experience

  8. CMM+ development Design of the new hardware, based on the schematics of the current CMM – PCB with all present interfaces and connectors plus SNAP12 sockets (for the new topological processor) and one large FPGA replacing one/two current FPGAs Adaptation of the current CMM firmware to the new hardware in order to provide full backward compatibility and test with the current system, test in the test rig In parallel - development of the new firmware for the CPM and JEM modules and the CMM+ for new functionality (including new data format), test in the test rig Merging two firmware in one and test in the test rig and in the current system; CMM+ will supply the data to the topological processor running in parallel with the current L1Calo system

  9. Simplified TP module block-diagram Housed in L1Calo CP/JP crate Optical ribbon links bring all L1 RoI data to each TP module Multiple modules can run in parallel on individual algorithm(s) Receive and preprocess data at quadrant level. Global processing of selected data Results transferred via backplane two merger modules (interfaces to CTP)

  10. TP module (TPM) development Housed in “standard” L1Calo CP/JP crate with backplane Up to 16 TP modules Can also house optical fan-out modules Several parts of the current L1Calo modules (e.g. - VME interface, TCM interface, ROD interface, Xilinx System ACE) – both schematics and firmware – can be reused to speed up the development of the TP module common part may be specified as a schematics and firmware while the actual PCB layout will be different for the CMM+ and the TP module equally valid for CMM+ Processing results are sent to 2 merger modules in the crate via existing lines at 160/320 MHz Two CMM+ can be used as merger modules with upgraded to 80 MHz legacy interfaces to CTPIN+ (4 connectors)

  11. TP system cabling 160/320 MBit/s CMM+ CMM+ TP modules (TPM) 6.5 GBit/s CMM+ CMM+ 4 CP crates 160 MBit/s MuonRoIs CMM+ CMM+ TP crate 80 MBit/s 2 JP crates Optical splitter To CTPIN+ 160 MBit/s

  12. Conclusions Be backward compatible and keep L1Calo trigger system running Develop of TP in parallel Minimize efforts Use as much as possible existing modules, crates, backplane, knowledge, experience and “IP” parts… Minimal modifications of existing interfaces to CPM and ROD Minimal upgrade of CMM to provide data for TP Use CPM/JEM crate with backplane, SBC, TCM to house TP modules and merge individual module results Use upgraded CMM as interface to CTP Don’t be too much ambitious  Aim new technology developments for Phase II

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