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Lecture 21

Lecture 21. OUTLINE The MOSFET (cont’d) P-channel MOSFET CMOS inverter analysis Sub-threshold current Small signal model Reading : Pierret 17.3; Hu 6.7, 7.2. P-Channel MOSFET. The PMOSFET turns on when V GS < V T Holes flow from SOURCE to DRAIN

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Lecture 21

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  1. Lecture 21 OUTLINE The MOSFET (cont’d) • P-channel MOSFET • CMOS inverter analysis • Sub-threshold current • Small signal model Reading: Pierret 17.3; Hu 6.7, 7.2

  2. P-Channel MOSFET • The PMOSFET turns on when VGS < VT • Holes flow from SOURCE to DRAIN  DRAIN is biased at a lower potential than the SOURCE • In a CMOS technology, the PMOS & NMOS threshold voltages are usually symmetric about 0, i.e.VTp = -VTn VG • VDS < 0 • IDS < 0 • |IDS| increases with • |VGS - VT| • |VDS| (linear region) VS VD GATE ID P+ P+ N VB EE130/230M Spring 2013 Lecture 21, Slide 2

  3. Long-Channel PMOSFET I-V • Linear region: • Saturation region: m = 1 + (3Toxe/WT) is the bulk-charge factor EE130/230M Spring 2013 Lecture 21, Slide 3

  4. VDD S G D VOUT VIN D G S CMOS Inverter: Intuitive Perspective SWITCH MODELS CIRCUIT VDD VDD Rp VOUT = 0V VOUT = VDD Rn Low static power consumption, since one MOSFET is always off in steady state VIN = VDD VIN = 0V EE130/230M Spring 2013 Lecture 21, Slide 4

  5. Voltage Transfer Characteristic N: sat P: sat VOUT N: off P: lin C VDD N: sat P: lin B D E A N: lin P: sat N: lin P: off 0 VIN VDD 0 EE130/230M Spring 2013 Lecture 21, Slide 5

  6. increasing VIN VDSp= - VDD VDSp= 0 CMOS Inverter Load-Line Analysis – VGSp=VIN-VDD + VIN= VDD+ VGSp – VDSp=VOUT-VDD + VOUT= VDD+ VDSp IDn=-IDp VIN= 0 V VIN= VDD IDn=-IDp increasing VIN VOUT=VDSn 0 VDD 0 EE130/230M Spring 2013 Lecture 21, Slide 6

  7. Load-Line Analysis: Region A – VGSp=VIN-VDD + – VDSp=VOUT-VDD + IDn=-IDp VIN VTn IDn=-IDp VOUT=VDSn 0 VDD 0 EE130/230M Spring 2013 Lecture 21, Slide 7

  8. Load-Line Analysis: Region B – VGSp=VIN-VDD + – VDSp=VOUT-VDD + IDn=-IDp IDn=-IDp VDD/2> VIN> VTn VOUT=VDSn 0 VDD 0 EE130/230M Spring 2013 Lecture 21, Slide 8

  9. Load-Line Analysis: Region D – VGSp=VIN-VDD + – VDSp=VOUT-VDD + IDn=-IDp IDn=-IDp VDD– |VTp| > VIN > VDD/2 VOUT=VDSn 0 VDD 0 EE130/230M Spring 2013 Lecture 21, Slide 9

  10. Load-Line Analysis: Region E – VGSp=VIN-VDD + – VDSp=VOUT-VDD + IDn=-IDp VIN > VDD– |VTp| IDn=-IDp VOUT=VDSn 0 VDD 0 EE130/230M Spring 2013 Lecture 21, Slide 10

  11. MOSFET Effective Drive Current, IEFF M. H. Na et al., IEDM Technical Digest, pp. 121-124, 2002 CMOS inverter chain: VDD V2 IH + IL V1 V2 V3 V3 tpLH IEFF = VDD/2 2 tpHL V1 TIME IDsat VIN = VDD CMOS inverter: VDD S IH D NMOS DRAIN CURRENT VOUT VIN D VIN = ½VDD S GND IL 0.5VDD VDD NMOS DRAIN VOLTAGE = VOUT EE130/230M Spring 2013 Lecture 21, Slide 11

  12. Propagation Delay, td VDD CMOS inverter chain: Voltage waveforms: VDD td is reduced by increasing IEFF and reducing load capacitance C EE130/230M Spring 2013 Lecture 21, Slide 12

  13. Sub-Threshold Current • For |VG| < |VT|, MOSFET current flow is limited by carrier diffusion into the channel region. • The electric potential in the channel region varies linearly with VG, according to the capacitive voltage divider formula: • As the potential barrier to diffusion increases linearly with decreasing VG, the diffusion current decreases exponentially: EE130/230M Spring 2013 Lecture 21, Slide 13

  14. Sub-Threshold Swing, S log ID NMOSFET Energy Band Profile n(E)  exp(-E/kT) Inverse slope is subthreshold swing, S [mV/dec] increasing E Source increasing VGS VGS Drain 0 VT distance EE130/230M Spring 2013 Lecture 21, Slide 14

  15. VT Design Trade-off • Low VT is desirable for high ON current: IDsat (VDD- VT) 1 <  < 2 • But high VT is needed for low OFF current: log ID Low VT • VT cannot be aggressively reduced! High VT IOFF,low VT IOFF,high VT VGS 0 EE130/230M Spring 2013 Lecture 21, Slide 15

  16. How to minimize S? EE130/230M Spring 2013 Lecture 21, Slide 16

  17. MOSFET Small Signal Model • Conductance parameters: A small change in VG or VDS will result in a small change in ID low-frequency: high-frequency: EE130/230M Spring 2013 Lecture 21, Slide 17

  18. Parasitic Components EE130/230M Spring 2013 Lecture 21, Slide 18

  19. MOSFET Cutoff Frequency, fT The cut-off frequency fT is defined as the frequency when the current gain is reduced to 1. • Higher MOSFET operating frequency is achieved by decreasing the channel length L vGhere is ac signal CG is approximately equal to the gate capacitance,  W L Cox input current = output current = At the cutoff frequency (wT= 2pfT): EE130/230M Spring 2013 Lecture 21, Slide 19

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