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TWEPP-07 Topical Workshop on Electronics for Particle Physics Prague 2007

TWEPP-07 Topical Workshop on Electronics for Particle Physics Prague 2007. Serial Powering of Silicon Sensors. E.G. Villani , M. Weber, M. Tyndel, R. Apsimon Rutherford Appleton Laboratory. Serial Powering scheme Characteristics of shunt regulator Experimental results Conclusions. Outline.

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TWEPP-07 Topical Workshop on Electronics for Particle Physics Prague 2007

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  1. TWEPP-07 Topical Workshop on Electronics for Particle Physics Prague 2007 Serial Powering of Silicon Sensors E.G. Villani, M. Weber, M. Tyndel, R. Apsimon Rutherford Appleton Laboratory

  2. Serial Powering scheme Characteristics of shunt regulator Experimental results Conclusions Outline

  3. Powering schemes comparison Efficiency:= Example of efficiency plot vs. number of modules (N) and supply voltage (V) for Im = 2 A Rc = 3 Ω for Serial Powering scheme PM = nImVm Pc = Im2Rc

  4. Serial powering diagram – module chain shunt regulation - Current source provides power to the chain of shunt regulators.Each of them provides power to the local modules.Communication is achieved through AC coupled LVDSEach sensor has individual HV bias, referenced to its ground ( this might not be necessary)Test structure built and tested with SCT modules Initial stave tests done by C. Haber at LBL

  5. Serial powering diagram – module shunt regulation -

  6. Regulators comparison • Series regulator can be thought of as a variable resistor in series with a load • Fluctuations in current drawn by the load modifies via the feedback the resistor values : the power supply sees a constant current load, current circulates back into the supply ↓Poor isolation ↑High efficiency ∆Ild • Shunt regulator can be thought of as a variable resistor in parallel with a load • Fluctuations in current drawn by the load modifies via the feedback the resistor values : the power supply sees a constant resistance, current does not circulate back into the supply ↑Good isolation ↓Low efficiency (Iloadmax to be provided by the supply) Shunt regulator advantageous for steady average current ∆Ild

  7. Serial powering circuitry evolution SSPPCB - 2006/7 - 38 mm x 9 mm SPPCB - 2006 - 111 mm x 83 mm • Hybrid • SSPPCB • ABCD3TV2 SPSCT - 2005 - 150 mm x 150 mm

  8. Serial powering stave implementation Initial stave work done by C. Haber LBNL

  9. Shunt regulator performances • The shunt regulator in SSPPCB01 built around standard • shunt TL431 • Output boosted using PNP D45H8. • The output is set to nominally 4V • Stability analysis, output impedance • Over current condition analysis

  10. Stability analysis • Phase margin vs. Ibias @ Resr [0.5, 2.5] Ω • Ibias decreases phase margin ( gm increases) • ESR affects forward feedback compensation ↑ESR OLG CLG

  11. Stability analysis Output noise with C1,C3 10 f 16 v ceramic X5R 0805 pack Oscillation bias dependent Tektronix TDS3044B 400 MHZ

  12. Stability analysis Output noise with C1,C3 10 f 16 v ceramic low ESR A pack Tektronix TDS3044B 400 MHZ Implication was size of low ESR capacitor ( A pack )

  13. A015 QL 355 TP AFG3252 Isink SSPPCB01 Hybrid WR6100A Output Impedance analysis Output impedance and phase measurement • Output impedance measured by applying a small sinusoidal varying signal to the driving current by means • of a current sink and measuring the corresponding output voltage. • From histogram of both peak-to-peak voltage and current the MPV value is determined • Their ratio is taken to determine the MPV of output impedance, in the frequency range of 1HZ to 40MHz. • From the histogram of the phase difference the output phase delay is measured in the same frequency range.

  14. Output Impedance analysis Current and voltage output @ f = 2 and 10MHz

  15. Output Impedance analysis Ω TL431 open loop gain • SSPPCB01 Shunt regulator output impedance module • | Zo| << 1ohm f<1MHz • Almost monotonic increase beyond 1MHz • Consistent with nominal Open loop gain characteristics of TL431

  16. Output Impedance analysis degrees Current and voltage output phase @ f = 20MHz • SSPPCB01 Shunt regulator output impedance phase • Arg( Zo) increases ≈ monotonically with frequency

  17. Output Impedance analysis • Low output impedance crucial to achieve good ‘grounding’ and reduce picked up noise • Feasible option of using single HV supply for several sensors SSSRi SRi SSSR1 SR1

  18. Shunt regulator protection analysis • The shunt regulator output has to carry the all current in case of load disconnected, to guarantee functioning of the chained modules • This condition implies a power dissipation by the shunt device directly proportional to its voltage output thus power wasted and risk of damage if not cooled or over dimensioned • A method investigated relies on automatically reducing shunt output voltage in case of overcurrent condition • This feature could also be digitally enabled to turn off a module

  19. Over current condition - Thermal analysis • Thermal analysis of SSPCB01 using IR camera 8…13μm • Simulated faulty condition: • No clock present onboard • No cooling • Different biasing conditions (400,500,600)mA Ibias 500mA Ibias 600mA emissivity of Si uncertain, used 0.75 * SSPPCB01 was left running at 700mA for 30mins. No change in performances or damaged observed afterwards.

  20. Shunt regulator protection scheme • The regulator automatically lowers its output voltage (from 4V to 1V in the test circuit) if the current through the power PNP continuously exceeds a set threshold for a set amount of time • The voltage output recovers with hysteresis ( ≈ 150mA in the test circuit) • The power pulse following an over currernt is not long enough to damage the PNP transistor • By proper design the power PNP is housed in SOT23 package, no heat sink needed

  21. Shunt regulator protection analysis Vout Isrct • voltage decreases from 4V to 1V within 3 ms following an over current (40mA to 1500mA) • voltage output recovers to 4V from1V (slew rate limited) within 70ms • with output voltage 1V the power dissipated by the PNP is ≈ 0.32W. Noise ≈ 2mV • circuitry left running for >1hr @ 1.5A. No damage or change in performances seen afterwards.

  22. Test results - SPSCT 2005 - Current source SP1 SCT1 SP2 SCT2 SP3 SCT3 SP4 SCT4 Photograph of test setup with 4 ATLAS SCT modules, serial powering scheme implemented on PCB. Average noise occupancies measured for four ATLAS SCT modules (top and bottom sensor average) • Test with up to 6 modules • Measure power saving and compare with predicted values

  23. Test results – SPPCB 2006 - • Average noise (ENC) for six SCT modules powered independently (IP) or in series (SP).

  24. Test results - SSPPCB 2007- • Tests on stave ongoing as modules are fitted • One chip not bonded • Noise (ENC) for two modules on stave (tests ongoing these days) • High voltage biasing scheme comparison: local (left) or shared (right) • No differences seen in noise performances

  25. Advantages Avoids matching problems between many parallel regulators Simplifies system and separates functions Allows for cheap MPW run for SMARP  reduce risk and accelerate powering R&D Chips could be used elsewhere (pixels/CMS) Next step – SMARP integrated solution - Linear regulator (optional) DCS including ADCs Power transistor (could be separate die) LVDS buffers Shunt regulator

  26. External serial powering chip Specifications based on experience with discrete solutions and verified by simulations The design could contain additional low voltage amplifiers to implement protection and slow control features Design will contain LVDS section Very generic power chip Vcs+ SOUT Sh sense P1 IN GMT U1 P2 FBS - VREF + PD GND U2 OPM - OPO OPP + /SEN P3 LOUT LIN LSense U3 LM - - FBL + + Next step – SMARP integrated solution -

  27. Conclusions • Reliability of Serial Powering demonstrated with several different designs of increasing compactness • Crucial advantages of Serial powering in power efficiency, cable, cost and material budget demonstrated • Various Serial Powering systems have been running since several years now; understanding of system properties well advanced and constantly progressing • Crucial features are dynamic characteristics of shunt regulator • Protection schemes devised, designed, built and successfully tested • Next crucial step is to design a custom general purpose ASIC (SMARP1), that could be a common ATLAS - CMS supply chip • Serial Powering scheme included in the design of future ATLAS SLHC Tracker Strip and Pixel Readout Chip

  28. Off-chip On-chip R 1.25 + Offset C + - 1.25 Backup slides – AC coupling - 120 MHz 40 MHz 1 MHz • Multi-drop configuration on stave

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