Study of CERN for the ALICE ITS upgrade

1. Study of CERN for the ALICE ITS upgrade KIM,D.H. , KWON,Y. ,SONG,M.K. Department of Semiconductor Science, DonggukUniv. for the ALICE collaboration. Department of Physics, Yonsei Univ. for the ALICE collaboration.

2. < CONTENTS > • Introduction • Explorer – study of pixel sensor • pALPIDE – study of front-end and readout • Conclusion • Appendix – work for ITS upgrade

3. I. Introduction - ALICE Inner Tracking System at present 2 layers of hybrid pixels (SPD) 2 layers of silicon drift detector (SDD) 2 layers of silicon strips (SSD)

4. I. Introduction - ITS upgrade – 7 layers

5. I. Introduction - Design specifications for PIXEL Chip (*) Assumptions: • Nr of bits to code a hit: 35 • Fake hit: 10-5 /event

6. I. Introduction - Technology • Commercial CMOS Imaging Sensor (CIS) • High resistivity epi layer • Deep p-well • Physical gate oxide thickness: 3 nm • Metal Option 6ML1 • 5 routing metals + 1 last metal for power busses

7. II. Explorer- PIXEL SENSOR OPTIMIZATION

8. II. Explorer- Prototype July 2012 submission: Explorer-0 • Analog readout for pixel characterization • Readout time decoupled from integration time • Possibility to reverse bias the substrate • Sequential readout with correlated double sampling • Contains two 1.8x1.8mm2 matrices of 20x20 and 30x30 micron pixels with different geometries PULSED ROWS

9. II. Explorer- Charge collection • Minimum Ionizing Particle (MIP) creates ~ 60 e/h pairs per micron of silicon traversed (in a thin layer) •  Example for 18 μm thick layer: 1200 e => 0.17 fC • Advantages of having collection by drift: • Tolerance to non ionizing radiation (less trapping probability) •  Reduction of the cluster size (less charge sharing)

10. II. Explorer- Explorer - Collection electrode layout nwell – spacing – pwell contact NMOS transistors in sectors 7, 8 and 9 are in a triple well.

11. II. Explorer- Block diagram • analog read-out for characterization studies • readout time decoupled from integration time • double readout in CDS mode RESET STORE1 STORE2 Pixel two independent analog memory cells, signal stored just after RESET and at the end of integration cycle circuit rowSelect columnSelect SEQUENCER … VDD + VSS + VPULSE analog biases BIAS PULSER column select OUT pixels read serially Periphery

12. II. Explorer- Explorer- circuit Features: • Serial readout. • Substrate bias < 0 V. • Tunable charge integration time.

13. III. pALPIDE- FRONT-END and READOUT

14. 0 512 III. pALPIDE- pALPIDE: prototype ALicePIxelDEtector STATE STATE STATE STATE 512 512 512 512 RESET RESET RESET RESET • in-matrix address encoder • tree structure to decrease capacitive load of lines • outputs pixel address and resets pixel storage element Pixel front-end Pixel front-end Pixel front-end Pixel front-end 512 512 512 512 Priority encoder Priority encoder • low power in-pixel discriminator • current comparator (bias of ~20 nA) • storage element for hit information 10 10 ADDR ADDR VALID VALID SELECT SELECT Periphery • loss-less data compression de-randomizing circuit • compresses cluster information in the column • multi-event memory Control + trigger Bias Clock Data Pulser

15. III. pALPIDE- IN-PIXEL HIT DISCRIMINATION Low Power Analog Front End (Power < 50 nW/pixel) based on a single stage amplifier/current comparator. Data driven readout of the pixel matrix, only zero-suppressed data are transferred to the periphery. Dynamic Memory Cell, Storage capacitor instead of SR-latch to save space.

16. III. pALPIDE- Front-End principle Low Power Analog Front End based on an weak inversion operation mode.  except current source transistor (M0, M4, M6) Ibias(20nA) Ithr(0.5nA) Idb(10nA)

17. III. pALPIDE- Front-End principle vsource vin vx vcurfeed voutb vout

18. III. pALPIDE- Front-End output example Front End output with a bias current of 20 nA

19. III. pALPIDE- Front-End output example Minimum detectable charge definition Memory state (V) Qin (electrons) Minimum detectable charge as a function of the bias current Cd = 1 fF Ith = 0.5 nA Ileak = 5 pA (nominal 20 nA condition)

20. III. pALPIDE- Priority Encoder readout PIXELCOLUMN • hierarchical readout • 4 inputs basic block repeated to create a larger encoder • 1 pixel read per clock cycle • forward path (address encoder) in gray • feed-back path (pixel reset) in red • asynchronous (combinatorial) logic • clock only to periphery, synchronous select only to hit pixels v[0] v[1] v[2] v[3] sel[0] sel[1] sel[2] sel[3] valid select a[0] a[1] v[0] v[1] v[2] v[3] sel[0] sel[1] sel[2] sel[3] valid select a[0] a[1] VALID v[0] v[1] v[2] v[3] sel[0] sel[1] sel[2] sel[3] valid select a[0] a[1] Periphery logic SELECT v[0] v[1] v[2] v[3] sel[0] sel[1] sel[2] sel[3] valid select a[0] a[1] CLOCK TRIGGER v[0] v[1] v[2] v[3] sel[0] sel[1] sel[2] sel[3] valid select a[0] a[1] ADDR[0:1] ADDR[2:3]

21. III. pALPIDE- Layout of pALPIDE FRONT-END Chip size: 30 mm x 15 mm Pixel size: 28 μm x 28 μm 1024 Columns x 512 Rows Collection Diode PIXEL LOGIC PRIORITY ENCODER Pixel Matrix: sensitive area State Memory I can‘t see information of Digital circuit  PRIORITY ENCODER, periphery readout logic, etc Periphery circuit ( DAC, PADs, periphery readout logic, etc)

22. IV. Conclusion Green : complete understanding Explorer PIXEL • Charge collection • - Diffusion, Drift • Design of collection electrode • - shape, nwell area, spacing … • Analysis about characteristic of each collection electrode Readout • Readout circuit • Rolling shutter architecture • Sequential readout with correlated double sampling • Asynchronous comparator • - operation principle ,weak inversion, noise analysis • Memory • Pixel Logic circuit pALPIDE Front-End • Priority Encoder • - Asynchronous logic, implement • Periphery readout logic • - synchronous select only to hit pixels, implement Readout • DAC & ADC • PLL • PAD • etc Periphery

23. IV. ConclusionBlue : weak understanding Explorer PIXEL • Charge collection • - Diffusion, Drift • Design of collection electrode • - shape, nwell area, spacing … • Analysis about characteristic of each collection electrode Readout • Readout circuit • Rolling shutter architecture • Sequential readout with correlated double sampling • Asynchronous comparator • - operation principle ,weak inversion, noise analysis • Memory • Pixel Logic circuit pALPIDE Front-End • Priority Encoder • - Asynchronous logic, implement • Periphery readout logic • - synchronous select only to hit pixels, implement Readout • DAC & ADC • PLL • PAD • etc Periphery

24. IV. ConclusionRed : didn’t understand Explorer PIXEL • Charge collection • - Diffusion, Drift • Design of collection electrode • - shape, nwell area, spacing … • Analysis about characteristic of each collection electrode Readout • Readout circuit • Rolling shutter architecture • Sequential readout with correlated double sampling • Asynchronous comparator • - operation principle ,weak inversion, noise analysis • Memory • Pixel Logic circuit pALPIDE Front-End • Priority Encoder • - Asynchronous logic, implement • Periphery readout logic • - synchronous select only to hit pixels, implement Readout • DAC & ADC • PLL • PAD • etc Periphery

25. IV. Conclusion • Study of pixel Studied the collection electrode. (shape, size, layout, etc)  But it was studied by Explorer result. So it needs to implement for more detailed analysis. • Analog readout circuit Studied the Front-end circuit. (operation principle)  But it was studied by simulation result. It needs to study an weak inversion operation mode in analog circuit for more detailed analysis of front-end circuit. • Digital readout circuit  I didn’t have a chance for study digital readout circuit.

26. Thank you

27. V. Appendix DAC - List of Voltage and Current DACs

28. VREF V. Appendix DAC – Voltage DAC • Block diagram & Simulation result AVSS <Voltage DAC resistor divider> <Voltage DAC unit block > <Voltage DACS output range at nominal corner simulation>

29. V. Appendix DAC – Monitoring & Overriding mode • Voltage DAC • Monitoring mode, external circuit requirement: • Measure a voltage value between 0 and VREF with a 10 bit resolution. • Read-out circuit with a high input impedance (Rin > 1 MΩ). • Overriding mode, external circuit requirement: • Set a voltage value on a high impedance net between 0 and VREF with a 8 bit resolution <Voltage DACs operation modes> <Voltage DACs: monitoring and overriding scheme>

30. 1 : 10 - Overriding reduction current mirror = 10 : 1 for bias currents 11 : 1 for IREF - Monitoring amplification current mirror = 1 : 10 Monitor or override a current in the 0 to 200 µA range V. Appendix DAC – Monitoring & Overriding mode PAD • Current DAC 0 to 20 A AVSS 1 : 10 • Monitoring mode, external circuit requirement: • Measure a current between 0 and 200 µA • Suggested load for the current measurement: ~ 5 kΩ (shunt between DACMONI and AVSS) • Overriding mode, external circuit requirement: • Set a current between 0 and 200 µA with a 9 bit resolution. • The current can be set with a tunable resistor between 5 kΩ and 5 MΩ (shunt between DACMONI and AVSS)

31. V. Appendix PIXEL– Input capacitance Reset diode capacitance Collection diode capacitance Routing capacitance <Front-End principle>

32. V. Appendix PIXEL– Input capacitance • Routing capacitance If –Av is 1 , Cm = 0 Input capacitance is can be compensated. <Miller effect> <pALPIDE Pixel Layout>

33. V. Appendix PIXEL– Input capacitance • Routing capacitance pALPIDE front-end circuit instead of Special source Follower to decrease input capacitance <Special Source Follower scheme>