TRIUMF Qweak Electronics

1. TRIUMF Qweak Electronics Des Ramsay Nov 2008

2. Status of Electronics • now five styles of preamp: Main: 0.5M, 1M, 2M, 4M, 26 kHz Lumi: 0.5M, 1M, 25M, 50M, 17 kHz KDP-A: 0.3M, 0.6M, 1.2M, 2.4M, 25 kHz KDP-B: 4k, 12k, 36k, 100k, 110 kHz SNS: 10k, 100k, 1M, 10M, 16 kHz • 36 VME modules (# 001 and # 003-037) delivered to JLab • 001, 003, 004, and 005 are back at TRIUMF for front-end upgrade. • 038 to Ohio (Paul) • 039 to U. Virginia (Kent) • 14 Main (0.5M, 1M, 2M, 4M) preamps to JLab • 14 Lumi (0.5M, 1M, 25M, 50M) preamps to JLab • 20 more preamps ordered by Roger. Insides ready at TRIUMF, need to be boxed and tested. • four KDP-A and four KDP-B ordered by Kent. November, 2008

3. Input Cables Large input capacitance increases the noise gain of the first stage. For Qweak we should limit the input cable capacitance to ~200 pf, for example 5m of RG-62. Some typical cables: TYPE Z0(ohm) C(pF/M) diameter(mm) RG-58 53 94.4 5.0 RG-62 93 44.3 6.2 RG-63 125 32.8 10.3

4. Issues to make sure we address • We need low capacitance cables for the preamp inputs 5 m, RG-62, 93  • We should not forget shielding of the preamps. • We need the same 20 MHz clock to all the integrators • Ideally, the spin flip should be synchronized with the clock • We may want the spin flip signal (“MPS”) in advance of the flip. • If we ground signals in the hall AND in the electronics cage we have to be sure we don’t get bad line noise. It’s easy to float one end, but is it allowed? • We need to test the actual noise early, with the full set-up and DAQ pattern. November, 2008

5. shot noise: Nature of the Current Mode Signals for Qweak 20 p.e. per event 50,000 e per event 1 M I-V 800 MHz VME digital signal integrator to DAQ 6.4 A 6.4 V x 2500 in shielding outside hall

6. Comparison of noise levels for Qweak 800 MHz event rate 20 p.e. per electron event PMT gain 2500 to give 6.4 mA 1 M preamp (6.4 volts to integrator) Electronic noise is small compared to counting statistics. The current source test would reach 10-9 (one ppb) in a day.

7. TRIUMF VME integrator details Ext NIM Gate Status LEDs VME Access Ext Clock Enb Ext Gate Enb 8 inputs Ext NIM Clock filter VME Module Select Switches ADC FPGA Prog/ Debug Ports DC-DC Converter FPGA

8. Simple description of VME Integrator • 8 channels, each takes a -10 to +10 volt signal. • Module triggered by external NIM signal (e.g. MPS) • Integrates for the selected time (up to 1/30 second) • Stores sum as 1,2,3, or 4 blocks plus the total sum • All modules are clocked by the same 20 MHz clock so all are exactly synched • Internally, 18-bit ADC runs at up to 500 ksps • 50 kHz sharp-cutoff analog anti-aliasing filter precedes ADC August, 2008

9. Location of adjustments on TRIUMF MK2 “main”-style preamp: M Chan 1 gain Offset adjust 4 2 1 0.5 Chan 1 IN Out Chan 2 0.5 1 2 4 +5 V DC Chan 2 gain M

10. Location of adjustments on TRIUMF MK2 “lumi”-style preamp: M Chan 1 gain Offset adjust 50 25 1 0.5 Chan 1 IN Out Chan 2 0.5 1 25 50 +5 V DC Chan 2 gain M

11. Simple description of TRIUMF preamp • Two channels per module • Four switch-selectable gain settings. • For Qweak main preamp Vout/Iin = 0.5, 1, 2, or 4 megohm • Output ±10 V. Adjustable ±2 V offset. Drives 130 m RG-213 • Noise referred to output = 0.5 with 5m of RG-62 on input • Power: 5 VDC Ground fully isolated by internal DC-DC converter. • BNC connectors for input and output. August, 2008

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13. Existing Ion Source Signals • Integration triggered by MPS • signals derived from 20 MHz crystal clock • Qweak integrator uses this clock as well

14. Averaging of Digitization Noise (we don’t want the analog bandwidth too low) • The 18 bit ADCs have ~0.5 LSB rms noise per sample. • This is reduced by averaging ~500 samples per integration. • This will only work if raw signal spreads over enough channels. • Assuming equivalent noise bandwidth 47 kHz (f3db= 30 kHz) and 18 bit ADC at mid range: • condition Q rms noise before channels channels • (e) integration () (FWHM) • beam ON 50,000 69 mV 1420 3339 • best possible 1 0.31 mV 6.3 15 • So this is OK even for very quiet signals. • Averaging makes integral equivalent to about 21 bits

15. Aliasing

16. Integral From Samples (we want the analog bandwidth low) • sample at the center of each interval (n samples) • Q = (sum of samples) x (t) • band limit signal to small fraction of sampling frequency to eliminate the wiggles and kinks. • we impose an analog cutoff at 1/10 the sampling frequency

17. Main VME registers • Sample Frequency = system clock / (PERIOD_MULT + 40) • 0 ≤ PERIOD_MULT ≤ 255 • Number of Blocks per integral (1,2,3, or 4) • Samples per Block : 1 ≤ SAMPLE_PER_BLOCK ≤ 16383 • Gate to Trigger Delay = 2.5 ms + (sample period x GATE_DELAY) 0 ≤ GATE_DELAY ≤ 255 • Gate Source: 0=internal, 1=external • System Clock Source: 0=internal, 1=external • Internal Gate Frequency = (100 kHz) / (INT_GATE_FREQ) 1 ≤ INT_GATE_FREQ ≤ 65535 • Individual block sums and total sum for each channel • Firmware Revision Date: REV_DATE always shows the release date of the current firmware revision running in the module August, 2008

18. Short description of VME Integrator • Quasi-differential isolated BNC connectors – 100 kW from BNC outer conductor to ground. • Input range -10 V to +10 V. Input impedance 12 KW. • Eight integrators per single width VME module. • Module clocked by 20 MHz signal from ion source. Sampling rate set as a fraction of the clock. Range 68 ksps to 500 ksps with 20 MHz clock. • Integration time software selectable – set as a fixed number of samples. (e.g. 2000 samples = 4 ms at 500 ksps) • Module gated by external NIM signal (e.g. MPS). Integration starts a selected time (gate-to-trigger delay) after the leading edge of the gate and runs for preset number of samples. • 32 bit overall sum available to the DAQ via VME bus. This sum can be divided into 1,2,3, or 4 sub- blocks (time intervals) as selected through VME. At full scale, the sum fills up in 1/30 s at 500 ksps. • Internal gate and internal 20 MHz clock provided for testing. • 50 kHz, 5-pole anti-aliasing filter • 18 bit ADC, sample rate up to 500 ksps • Buffered output permits reading previous integral during integration. • Crate power 0.5 A at +12 V and 1.0 A at +5 V August, 2008

19. Firmware Running Modes • Integration starts at the preset time (set via VME) after the gate. • We have tried three modes: • No conversion until gate received. • Continuous conversion – integration starts at next sample period. • Continuous conversion, but timing is re-synched on each gate. • We noticed, for 4 ms integrals, 500 ksps, and 4 x 1 ms blocks: • Mode 1 – first block in four block integral was low (~25 mV). • Mode 2 – no difference in blocks, but phase of two modules coulddiffer by half a sample period (1 ms at our 500 ksps). • Mode 3 – initially seemed to solve both problems, but with long runs,detected small residual block difference (1.5 mV with500-sample blocks). Neither the block offset or small time offset can affect the asymmetry Nevertheless, it looks like we can eliminate both by using scheme 3with sufficient gate-to-trigger delay.

20. current helicity - + - + - + - 6 A 3.6 pA (0.6 ppm p-p) ( ppm) time Size of Qweak Signal • figure shows regular spin flip; in practice use + - - + or - + + - • for 50 kHz noise bandwidth, rms shot noise is 70 nA • on a scope the noise band would be  100,000 x the signal !

21. TRIUMF VME integrator component side: solder side:

22. VME Integrator Front End Quasi-differential Full-differential

23. Location of adjustments on TRIUMF SNS preamp: Chan 1 gain Offset adjust Chan 1 Out IN Chan 2 +5 V DC Chan 2 gain

24. Changing gains and offset on the TRIUMF SNS preamp increasegain increasegain • To open the preamp for adjustment, remove the hex nuts from the OUTPUT side and remove the black screws from the INPUT side. • The rotary gain switches are used to select gain of 10k, 100k, 1M, or 10M. Turn the switch counter-clockwise to increase the gain. • The offset is set for 1.0 volts when shipped, but can be changed with the offset adjust pot.

25. + + - - Signal loss at start of spin states • If polarization has not settled by start of integration, some signal is lost • In the case of the above (+ - - +) quartet, more (+) is lost than (-) • For the parity signal itself, this is only a small part of an already small signal and is likely OK • In the case of helicity correlated current or position it may be a problem

26. E497 DAQ Sequence for One Spin State

28. 150 MW I to V Amplifier

29. Integral From Samples (trapezoidal rule) • sample at the sides of each interval (n+1 samples) • Q = (average of first and last samples plus sum of others) x (t) • band limit signal to small fraction of sampling frequency to eliminate the wiggles and kinks. • we impose an analog cutoff at 1/10 the sampling frequency

30. equivalent noise bandwidth [Hz] or [A2] one-sided shot noise, charge quantum [C] current [A] Shot Noise Recap Example, 1 ms integration with beam on, assuming 800 MHz: • Q = 50,000 e • I = 6.4 A (800 MHz x 50,000 e) • B = 500 Hz • in = 7.2 nA rms (7.2 mV with a 1 M preamp) Note that in 1 ms, N = 8 x 105 counts. = 1120 ppm, same as 7.2 nA/6.4 A