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What is µP?

What is µP?. “An integrated circuit containing … a central processing unit (CPU) and a means to access external memory” -- (Ball 2000). 0. 0. x. 1. 1. x. x. 1. x y. y. Memory. Memory types RAM ROM, PROM EPROM, EEPROM, Flash RAM Memory Cell inactive read write. Bus.

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What is µP?

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  1. What is µP? • “An integrated circuit containing … a central processing unit (CPU) and a means to access external memory” -- (Ball 2000)

  2. 0 0 x 1 1 x x 1 x y y Memory • Memory types • RAM • ROM, PROM • EPROM, EEPROM, Flash • RAM Memory Cell inactive read write

  3. Bus • Collection of signal lines -- uni(bi)directional • Operation represented using timing diagrams • Clocked vs Asynchronous separate data and address buses

  4. System Bus Control Signals • Multiple users? • arbitration • sender/reciever id • Multiplexed? • data ready • clock • Block Transfer • busy PCI Bus -- Read

  5. VonNeumann code can be modified (accidentally) Harvard data access does not slow code access instruction and data widths unrelated CPU Architecture Data Code Data Code Data CPU Code CPU Data

  6. CPU Internals Registers: Storage for data ALU: manipulates data in response to signals from the control unit Control Unit: issues control path signals (micro-operations) to other parts of CPU Bus: Transports data between ALU and registers

  7. 2 1 3 1 0 2 1 0 0 1 3 0 3 1 1 CPU Architecture Accumulator Stack Register Ra=1; Rb=2; Ra=Ra+Rb; w=1; w=w+2; Push 1 Push 2 Add

  8. Instruction vs. Micro-operation Write

  9. Address Pnemonic Value 1100 load 1 00 0001 1101 add 5 10 0101 1110 jmp 1100 ………. 1101 10 0101 0001 1101 1110 2 1 1 PC CU IR 3 3 00 0001 10 0101 Add Instruction - Fetch

  10. 1 ALU operation 0 add 0 bit 3 1 bit 2 0 bit 1 1 bit 0 0101 IR CU Add Instruction - Indirect (Decode) Control signals

  11. 1 0001 ALU 2 3 1 3 CU 1 1 0101 Add Instruction - Execute 0110 add Status flags

  12. Single-cycle instruction execution Simple, fixed instruction format few instructions and addressing modes Hardwired micro-operations Memory Access Load/Store design High-performance memory (registers/cache). Predictable Speed/Performance Multi-cycle instruction execution Variable size instruction format Micro-programmed instruction set Smaller program size (# of instructions) Memory Access Multiple addressing modes Optimization Complexity RISC vs. CISC

  13. Fetch4 Fetch1 Fetch5 Fetch3 Fetch2 Fetch2 Fetch1 Indirect2 Indirect1 Indirect1 Indirect2 Indirect5 Indirect3 Indirect4 Execute2 Execute5 Execute4 Execute1 Execute1 Execute3 Execute2 Write4 Write2 Write1 Write5 Write2 Write3 Write1 Pipelining • Assumptions: • stages all have same duration • no branching • consecutive instructions are independent

  14. Bit Widths Instruction set CPU components bus operations parallel/replicated functions? Pipelining RISC/CISC Control signals Micro-operation set external interface access times RAM: static vs. dynamic physical layout manufacturing process logic family track length power/heat considerations Architecture vs. Organisation

  15. Machine Instructions Data transfer Move register register Store register memory Load memory register Exchange register register Swap lo-nibble hi-nibble Clear 00000000 register Set 11111111 register Push register stack Pop stack register

  16. register register OP register Machine Instructions Arithmetic/Logical increment, decrement, not absolute, negate, two’s-complement add, subtract, multiply, divide and, or, exclusive-or register register

  17. ··· ··· ··· ··· Machine Instructions:Bit--Logical x Bit-set, Bit-clear Bit-test Bit-compare Shift == x? y ? x == Rotate

  18. Program flow skip [PC]=[PC]+1 branch [PC]=? call push [PC]; [PC]=? return pop [PC] Processing pause nop 1 cycle delay sleep wait for event wait ? cycle delay Special: input/output data conversion system operation Compound conditional branch IF BIT-TST BRANCH return with value LOAD VALUE RETURN Machine Instructions Control transfer/Special purpose

  19. Add Load Branch Arithmetic Data Transfer Control Transfer Machine Instruction Examples Address Mnemonic Value 1100 load 1 00 0001 1101 add 5 10 0101 1110 jmp 12 01 1110 Operand 4 bits Op-code 2 bits

  20. Addressing Modes Displacement Variants Relative Base Register Indexing Post-Indexing Pre-Indexing

  21. 0-operand PUSH 5 PUSH 6 ADD 2-operand LOAD R1,5 ADD R1, 6 1-operand LOAD 5 ADD 6 3-operand LOAD R2, 5 ADD R1, R1, R2 Register Stack Accumulator How Many Operands?

  22. Variable length instructions,Operand Specified Addressing Modes

  23. Branch 0100 0000 Operating System 0100 Load 5 Add 2 0101 …... 0110 1110 End System Reset / Program Launch Start Halt

  24. Development Software Tool Chain IDE Editor Compiler Simulator Linker Download Program Live In-circuit Debugger

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