ECE 8053 – Project Fall’02

1. ECE 8053 – Project Fall’02 Design of 64-bit Low Power Spanning Tree Carry Lookahead Adder Presented by Suderson Soundararajan

2. Overview • Introduction • Design • Optimization for Power • Optimization for Performance • Optimization for Area • Usage of CAD tools • Presentation of Results and Comparison • Summary and Conclusion • References

3. Design

4. Optimization for Power • Low Power and High Performance Full Adder Cell Full Adder Cell – A Novel High Performance CMOS 1-bit Full Adder cell, Ahmed M.Shams, Bayoumi, M.A

5. Optimization for Speed • Domino! • Two-Phase Clock – Generated using Chopper Circuit

6. MCC – Group Propagate Signal Generation MCC – Group Generate Signal Generation Optimization for Speed Contd..

7. Optimization for Area 4-bit Carry Select Adder - Youngjoon Kim; Lee-Sup Kim. “A Low Power Carry Select adder with Reduced Area” Less Number of Transistors => Less Area

8. MCC Blocks MCC3 MCC2 Delay 420 ps 300 ps Power 15 uW 11 uW Delay and Power Dissipation

9. Usage of CAD tools • Functionality Verification - Gate Level Verilog – ModelSim • Synthesis - Flattened Netlist – Synopsys • Transistor Level Simulation and Testing - Netlist - Cadence Spectre

10. Results Comparison

11. Conclusion • Achieved Low Power and High Performance compared to the conventional one • Can still optimize for Power – Carry Lookahead Scheme • Can still optimize for Speed – Sizing!

12. References • Thomas Lynch, Earl E.Swartzlander, “A Spanning Tree Carry Lookahead Adder,” IEEE transactions, Vol 41, No.8, August 1992. • Jeffrey Blackburn, Lisa Amdt, Earl E.Swartzlander, “Optimization of Carry Lookahead Adders”, 1997, IEEE transactions. • Ahmed M.Shams, Bayoumi, M.A, “A Novel High Performance CMOS 1-bit Full Adder Cell”, IEEE transactions, Vol.47, No.5, May’2000. • Youngjoon Kim; Lee-Sup Kim. “A Low Power Carry Select adder with Reduced Area, Circuits and Systems,” ISCAS 2001. The 2001 IEEE International Symposium on, Volume: 4, 2001 Page(s): 218 –221