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Introduction to Computer Systems

Introduction to Computer Systems. Lecturer: Steve Maybank Department of Computer Science and Information Systems sjmaybank@dcs.bbk.ac.uk Autumn 2014 Week 6b: Types of Instruction. Machine Architecture. Main memory. Central processing unit. Arithmetic/ logic unit. Address | Cells.

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Introduction to Computer Systems

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  1. Introduction to Computer Systems Lecturer: Steve Maybank Department of Computer Science and Information Systems sjmaybank@dcs.bbk.ac.uk Autumn 2014 Week 6b: Types of Instruction Birkbeck College, U. London

  2. Machine Architecture Main memory Central processing unit Arithmetic/ logic unit Address | Cells Registers 00 0 1 Program counter 01 Bus . . . . Control unit Instruction register FF F Brookshear, Section 2.2

  3. Machine Language Concepts • Registers (R, S, T…) • Memory addresses • Number of bytes in a memory cell • Instruction • Sequence of instructions • Branching (choice of next instruction) Brookshear, Section 2.2

  4. Properties of the Illustrative Machine • No. memory cells: 256 • No. bits in a memory cell: 8 (1 byte) • No. registers: 16 • No. bits in a register: 8 (1 byte) • No. bits in the programme counter: 8 (1 byte) • No. bits in the instruction register: 16 (2 bytes) Birkbeck College, U. London

  5. Illustrative Machine Language Brookshear, Appendix C

  6. Illustrative Machine Language Brookshear, Appendix C

  7. Types of Instruction • Data transfer LOAD, STORE, MOVE • Arithmetic/Logic ADD, OR, AND, XOR, ROTATE • Control JUMP, HALT Brookshear, Section 2.2

  8. Format of an Instruction • Instruction=op-code field+operand field • Op-code: identifies the elementary operation, e.g. STORE, SHIFT, XOR, JUMP. • Operand: additional information, e.g. data or a register address. Brookshear, Section 2.2

  9. Instruction 156C Op-code 1: load Register with bit pattern in memory at the given address memory address register Brookshear, Section 2.3

  10. Op Code 7 (OR) 1st register OR 2nd register = 3rd register Brookshear, Section 2.3

  11. Op Code A (Rotate right) register rotate right 1 rotate right 2 Brookshear, Section 2.3

  12. Instruction B258 Op-code B: change value of program counter if contents of indicated register = contents of register 0 New contents of program counter Indicated register Brookshear, Fig. 2.9. Brookshear, Section 2.3

  13. Machine Cycle Fetch next instruction from memory to the CPU Decode the instruction Fetch Decode Execute Execute the instruction Brookshear, Section 2.3

  14. First Part of the Fetch Step of the Machine Cycle Main memory CPU address cells program counter 15 6C 16 6D A0 A1 A2 A3 bus instruction register Brookshear, Section 2.3

  15. Completion of the Fetch Step Main memory CPU address cells program counter 15 6C 16 6D A0 A1 A2 A3 bus instruction register Brookshear, Section 2.3

  16. Updating the Program Counter • Fixed length instructions (2 bytes). • Instructions stored consecutively in main memory. • Each memory cell holds 1 byte. • Then pc pc + 2 at the end of each Fetch. memory … 5 6 7 8 9 10 11 12 13 14 … pc=7 Brookshear, Section 2.3

  17. Program to Add Two Values • Get the first value from memory and place it in a register S. • Get the second value from memory and place it in another register T. • Add the contents of S, T and place the result in a register R. • Store the result in R in memory • Stop Brookshear, Section 2.3

  18. Encoded Program • 156C. Load register 5 with the contents of memory cell 6C. • 166D. Load register 6 with the contents of memory cell 6D • 5056. Add (2s comp) contents of registers 5, 6. Put result in register 0. • 306E. Store the contents of Register 0 at memory cell 6E. • C000. Halt. Brookshear, Section 2.3

  19. Without Instruction B • A program containing n instructions would run for n-1 machine cycles. • The program would be unable to respond to changes in the data. Birkbeck College, U. London

  20. Fibonacci Numbers • 0,1,1,2,3,5,8,13,21,34,55, … • N(1)=0, N(2)=1 • N(i+1)=N(i)+N(i-1) for i=2,3,4, … Birkbeck College, U. London

  21. Program to Find the 10th Fibonacci Number 20 2000 // load register 0 with 0 22 2100 // load register 1 with 0 24 2201 // load register 2 with 1 26 2408 // load register 4 with 8 28 25FF // load register 5 with -1 (Two’s Comp) Address Instruction Comment R4 R5 R3 R1 R0 R2 08 FF 00 00 01 ** Birkbeck College, U. London

  22. Program to Find the 10th Fibonacci Number Address Instruction Comment 2A 5312 // Add contents of R1, R2. Put result in R3 3C 4021 // Move bit pattern in R2 to R1 2E 4032 // Move bit pattern in R3 to R2 30 5445 // Add contents of R4, R5. Put result in R4 32 B436 // If contents R4=contents R0, go to 36 34 B02A // If contents R0=contents R0, go to 2A 36 C000 // Halt. Result is in R2. Birkbeck College, U. London

  23. Assembly Language • Mnemonic system for representing machine language Machine language 156C 166D 5056 306E C000 Assembly language LD R5, Price LD R6, ShippingCharge ADDI R0, R5, R6 St R0, TotalCost HLT Brookshear, Section 6.1

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