1 / 5

YB825

YB825. 3 wafer batch for NYU/STT July 21, 2010 Jordan Katine. Wafer Film Stacks. SWS2140 MTJ 30 Ta/600 Cu/50 Ta/20 Pd/20 CoPd/22 CoNi/100 Cu/30 CoFeB/10 MgO/23 CoFeB/9 Ru/20 CoFe/160 PtMn/100 Cu/70 Ru/30 Ta SWS2136 pinned SV

waseem
Download Presentation

YB825

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. YB825 3 wafer batch for NYU/STT July 21, 2010 Jordan Katine

  2. Wafer Film Stacks SWS2140 MTJ 30 Ta/600 Cu/50 Ta/20 Pd/20 CoPd/22 CoNi/100 Cu/30 CoFeB/10 MgO/23 CoFeB/9 Ru/20 CoFe/160 PtMn/100 Cu/70 Ru/30 Ta SWS2136 pinned SV 30 Ta/600 Cu/50 Ta/20 Pd/20 CoPd/22 CoNi/100 Cu/30 CoFeB/100 Cu/23 CoFeB/9 Ru/20 CoFe/160 PtMn/100 Cu/70 Ru/30 Ta SWS2129 SV 30 Ta/600 Cu/50 Ta/20 Pd/20 CoPd/22 CoNi/100 Cu/30 CoFeB/100 Cu/120 CoFeB/100 Cu/70 Ru/30 Ta

  3. Device Matrix Col. # x (nm) y(nm) Shape 1 60 4000 TEM test site 2 40 80 Ellipse 3 40 100 Ellipse 4 40 120 Ellipse 5 50 100 Rectangle 6 50 100 Ellipse 7 50 100 Hexagon 8 50 150 Rectangle 9 50 150 Ellipse 10 50 150 Hexagon 11 60 120 Rectangle 12 60 120 Ellipse 13 60 120 Hexagon 14 60 180 Rectangle 15 60 180 Ellipse 16 60 180 Hexagon 17 80 160 Rectangle 18 80 160 Ellipse 19 80 160 Hexagon 20 80 240 Ellipse 21 80 240 Hexagon

  4. Wafer Layout Yes Yes Yes Yes Yes Yes Annealing Direction Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Only chips labeled “Yes” were exposed in the e-beam tool. Unshaded chips should all be open devices, i.e. nearly infinite resistance.

  5. Wafer Layout a3 Yes Yes Yes b3 c3 Annealing Direction Yes Yes Yes d3 e3 f3 Yes Yes Yes g3 h3 Only chips labeled “Yes” were exposed in the e-beam tool. Unshaded chips should all be open devices, i.e. nearly infinite resistance.

More Related