CMPT 300 Introduction to Operating Systems

1. CMPT 300Introduction to Operating Systems Page Replacement Sample Questions

2. True or False I • Q: Adding more RAM always reduces the number of page faults that occur in a system. • A: False - See Belady's Anomaly. This can occur with FIFO replacement. One can come up with an example of page accesses that actually result in an increase in the amount of page faults; however, most systems probably use a better replacement policy and Belady's Anomaly is probably not the common case - so do not let that dissuade you from purchasing additional RAM.

3. True or False II • Q: Compulsory misses can be reduced by prefetching data before they are used. • A: True - If access pattern consists of reading data sequentially, then by prefetching large blocks of data in advance, I can reduce the number of cache misses/page faults as the next piece of data I want to read will have already been loaded ready for use.

4. True or False III • Q: Compulsory misses can be reduced by prefetching data before they are used. • A: True - If access pattern consists of reading data sequentially, then by prefetching large blocks of data in advance, I can reduce the number of cache misses/page faults as the next piece of data I want to read will have already been loaded ready for use.

5. True or False IV • Q: The LRU Algorithm always replaces the oldest page on a page fault, where age is defined by amount of time the page has been in RAM. • A: False. FIFO does that.

6. Degree of MultiProgramming • Q: Consider a demand-paged computer system where the degree of multiprogramming (# of concurrently running processes) is currently fixed at four. The system was recently measured to determine utilization of CPU and the paging disk. The results are one of the following alternatives. For each case, can the degree of multiprogramming be increased to increase the CPU utilization? • a. CPU utilization 13 percent; disk utilization 97 percent • b. CPU utilization 87 percent; disk utilization 3 percent • c. CPU utilization 13 percent; disk utilization 3 percent • A: a. Thrashing is occurring. Should decrease degree of multiprogramming • b. CPU utilization is sufficiently high to leave things alone. • c. Can increase the degree of multiprogramming.

7. Bounds • Assume a stream of page references with length p, containing n distinct Physical Page Numbers (PPNs) occurring in it. Assuming the physical memory has m memory frames (initially all empty). For any page-replacement algorithm, what is the lower bound & upper bound on the number of page faults? (assuming m >= n). • A: lower bound: n; upper bound: p

8. Page Replacement I • Q: Consider a two-dimensional array A: int A[][] = new int[100][100]; where A[0][0] is at location 200 bytes, in a paged system with pages of size 200 bytes. (The page sizes are unrealistic; for illustration purposes only.) A small process is in page 1 (locations 0 to 199) for manipulating the matrix; thus, every instruction fetch will be from page 0. Assuming the matrix is stored in row-major order, i.e., each row is stored one after another. For a physical memory of 3 page frames, how many page faults are generated by the following array initialization loops, using LRU replacement, and assuming page frame 1 has the process in it, and the other two are initially empty (assuming 16-bit integer): • A: for (int j = 0; j < 100; j++) • for (inti = 0; i < 100; i++) A[i][j] = 0; • B: for (inti = 0; i < 100; i++) • for (int j = 0; j < 100; j++) A[i][j] = 0; • Answer: An int is 2 bytes and each page has length 200 bytes. Then each row of array A (100 ints) fits exactly in a page. Algorithm A processes one column at a time, hence it generates a page fault at every inner loop iteration, with a total of 100*100=10,000 page faults. Algorithm B processes one row at a time, hence it generates a page fault at every outer loop iteration, with a total of 100 page faults. So algorithm B has better spatial locality. Note that page replacement algorithm doesn’t matter here since the physical memory is so small.

9. Illustration • Consider a 4x4 array example. Each row fits in a page. Algorithm B walks the array one row at a time (left), while Algorithm A walks the array one column at a time. 0 1 2 3 0 1 2 3 Page 1 Page 1 0 0 1 1 Page 2 Page 2 2 2 Page 3 Page 3 3 3 Page 4 Page 4 Algorithm B Algorithm A

10. Page Replacement II • Consider a physical memory with 3 page frames. Each column represents a time-step. If there is no page fault during that time-step, leave the column blank. Consider FIFO, OPT, LRU, and CLOCK.

11. FIFO • 13 page faults

12. OPT • 9 page faults (the last two page faults could choose to replace any physical page.)

13. LRU • 12 page faults

14. CLOCK • 12 page faults

15. Page Replacement III • Consider a physical memory with 3 page frames. Each column represents a time-step. If there is no page fault during that time-step, leave the column blank. Consider FIFO, OPT, LRU, and CLOCK.

16. FIFO • 11 page faults

17. LRU • 10 page faults

18. CLOCK • 10 Page faults.