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Nội dung môn học

Nội dung môn học. Giới thiệu chung về hệ vi xử lý Bộ vi xử lý Intel 8088/8086 Lập trình hợp ngữ cho 8086 Tổ chức vào ra dữ liệu Ngắt và xử lý ngắt Truy cập bộ nhớ trực tiếp DMA Các bộ vi xử lý trên thực tế. Chương 6: Truy cập bộ nhớ trực tiếp DMA. Giới thiệu về DMA

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Nội dung môn học

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  1. Nội dung môn học • Giới thiệu chung về hệ vi xử lý • Bộ vi xử lý Intel 8088/8086 • Lập trình hợp ngữ cho 8086 • Tổ chức vào ra dữ liệu • Ngắt và xử lý ngắt • Truy cập bộ nhớ trực tiếp DMA • Các bộ vi xử lý trên thực tế

  2. Chương 6: Truy cập bộ nhớ trực tiếp DMA • Giới thiệu về DMA • Mạch DMAC 8237A của Intel

  3. Giới thiệu về DMA

  4. Mạch DMAC 8237A của Intel

  5. Mạch DMAC 8237A của Intel • Although i8237A may not appear as a discrete component in recent PCs, it’s still there… (integrated in chipsets, ISPC) • The i8237A has four independent DMA channels • Original PC/XT design had one i8237A for four DMA channels • PC/AT used two i8237As to provide 7 DMA channels • i8237A is programmable device and can be configured for single transfers, block transfers, Reads, Writes or Memory-to-Memory transfers 

  6. Mạch DMAC 8237A của Intel • i8237A allows byte addressing for 8-bit data transfers • In the PC/AT design, a contrived 16-bit transfer design is implemented using the i8237A  • i8237A uses a multiplexed address and data bus to reduce the device pin count. • DB0..DB7 lines contain the data bus along with the high byte of the 16-bit address bus. • An external latch is required to demultiplex the address lines

  7. Mạch DMAC 8237A của Intel

  8. Mạch DMAC 8237A của Intel

  9. Mạch DMAC 8237A của Intel

  10. How the PC uses the i8237A

  11. DMA Address Tracking • The i8237A has four registers for tracking memory addresses during a DMA block • BASE ADDRESS REGISTER • BASE WORD COUNT REGISTER • CURRENT ADDRESS REGISTER • CURRENT WORD COUNT REGISTER

  12. DMA in the PC/XT

  13. Cascaded i8237As in the PC/AT DMA Cascadation

  14. PC/AT DMA Channel priorities • DMA channel 0 (DREQ0) has the highest priority • DMA channel 7 (DREQ7) has the lowest • Note, when a DMA transfer is in session, it cannot be 'interrupted' by another DMA request, even if the DMA request is made by a higher priority DMA channel. • The current DMA transfer session will be completed before the pending DMA request is accepted

  15. DMA Channels in the PC/AT DMA Priority Pre-defined 8-bit or Use in PC/AT 16-bit ____________________________________________________________ DREQ0 Highest Memory Refresh* 8-bits DREQ1 Not defined 8-bits DREQ2 Floppy Disk 8-bits DREQ3 Not defined 8-bits DREQ4 Cascade not used DREQ5 Not defined 16-bits DREQ6 Not defined 16-bits DREQ7 Lowest Not defined 16-bits

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