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Normal operation

Normal operation. A. B. C. ACLK (32.768kHz). Timer count (ex. TA0R). 5. 6. 7. 0. 1. Interrupt. CCR1 Interrupt. overflow Interrupt. CCR2 Interrupt. Note: Timer Settings : Upmode / CCR0=7 / CCR1 =7/ CCR2=1 Interrupts Enabled: CCR1/CCR2/overflow.

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Normal operation

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  1. Normal operation A B C ACLK (32.768kHz) Timer count (ex. TA0R) 5 6 7 0 1 Interrupt CCR1 Interrupt overflow Interrupt CCR2 Interrupt Note: Timer Settings : Upmode / CCR0=7 / CCR1 =7/ CCR2=1 Interrupts Enabled: CCR1/CCR2/overflow

  2. Case A: Pattern1Timer is cleared in A duration command : TA0CTL |= (MC_1 | TACLR); Timer Clear ACLK (32.768kHz) Timer count (ex. TA0R) 5 6 7 0 1 0 Interrupt CCR1 Interrupt overflow Interrupt CCR2 Interrupt

  3. Case A: Pattern 2Timer is cleared in A duration command : TA0CTL |= (MC_1 | TACLR); Timer Clear ACLK (32.768kHz) Timer count (ex. TA0R) 5 6 7 0 0 Interrupt CCR2 Interrupt CCR1 Interrupt overflow Interrupt

  4. Case B: Pattern 1Timer is cleared in B duration command : TA0CTL |= (MC_1 | TACLR); Timer Clear ACLK (32.768kHz) Timer count (ex. TA0R) 5 6 7 0 2 1 Interrupt CCR1 Interrupt CCR2 Interrupt

  5. Case B: Pattern2Timer is cleared in B duration command : TA0CTL |= (MC_1 | TACLR); Timer Clear ACLK (32.768kHz) Timer count (ex. TA0R) 5 6 7 0 0 1 Interrupt CCR2 Interrupt CCR1 Interrupt

  6. Case B: Pattern3Timer is cleared in B duration command : TA0CTL |= (MC_1 | TACLR); Timer Clear ACLK (32.768kHz) Timer count (ex. TA0R) 5 6 7 0 1 Interrupt CCR2 Interrupt CCR1 Interrupt

  7. Case B: Pattern4Timer is cleared in B duration command : TA0CTL |= (MC_1 | TACLR); Timer Clear ACLK (32.768kHz) Timer count (ex. TA0R) 5 6 7 1 2 Interrupt CCR2 Interrupt CCR1 Interrupt

  8. Case C: Pattern 1Timer is cleared in C duration command : TA0CTL |= (MC_1 | TACLR); Timer Clear ACLK (32.768kHz) Timer count (ex. TA0R) 0 5 6 7 1 2 Interrupt CCR1 Interrupt CCR2 Interrupt

  9. Case C: Pattern 2Timer is cleared in C duration command : TA0CTL |= (MC_1 | TACLR); Timer Clear ACLK (32.768kHz) Timer count (ex. TA0R) 0 5 6 7 0 1 Interrupt CCR2 Interrupt CCR1 Interrupt

  10. Case C: Pattern3Timer is cleared in C duration command : TA0CTL |= (MC_1 | TACLR); Timer Clear ACLK (32.768kHz) Timer count (ex. TA0R) 5 6 7 0 2 1 Interrupt CCR2 Interrupt CCR1 Interrupt

  11. Case C: Pattern4Timer is cleared in C duration command : TA0CTL |= (MC_1 | TACLR); Timer Clear ACLK (32.768kHz) Timer count (ex. TA0R) 5 6 7 0 1 0 Interrupt CCR2 Interrupt CCR1 Interrupt

  12. Case C: Pattern5Timer is cleared in C duration command : TA0CTL |= (MC_1 | TACLR); Timer Clear ACLK (32.768kHz) Timer count (ex. TA0R) 5 6 7 1 2 Interrupt CCR2 Interrupt CCR1 Interrupt

  13. Case C: Pattern6Timer is cleared in C duration command : TA0CTL |= (MC_1 | TACLR); Timer Clear ACLK (32.768kHz) Timer count (ex. TA0R) 5 6 7 0 1 Interrupt CCR2 Interrupt CCR1 Interrupt

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