3. Advanced Rules & Models

1. 3. Advanced Rules & Models Etienne Sicard etienne.sicard@insa-tlse.fr http://intrage.insa-tlse.fr/~etienne

2. Summary • New design rules • MOS models (Model 1, 3, bsim4) • Interconnect model • Crosstalk model • Conclusion

3. 1. New design rules • By default salicide deposit • Low resistance N+,P+ and poly surface • Removing salicide increases the resistance Protect from Salicide Default salicide deposit

4. 1. New design rules • Lateral Drain diffusion prevents hot carrier damage • Hot carriers degrade Vt, IdSat (10% less than 1 year without LDD) • ESD is improved without LDD LDD

5. 1. New design rules • During fabrication, plasma etching charges metal lines • Charges degrade MOS Vt, or damage oxide • Charges must be eliminated to the substrate Charges accumulated Gate damage Antenna ratio = Area (metal)/Area(gate) Do It Solution: Add diodes

6. Scoop The MOS model 1 works fine in 0.35µm (Shockley, 1950) 2. MOS model Measured 10x10µm in 0.35µm ST (hcmos6)

7. Sad, sad 150% No MOS level 1 in design rule manuals 2. MOS model 10x0.4 µm in 0.35µm ST (hcmos6) MOS model 1 gives 150% error for L=0.35µm (Shokley, 1950)

8. 2. MOS model Measure simulation MOS level 3 includes short channel limitation effects MOS 3 is considered obsolete starting 0.5µm, but is still in used for first-order estimations

9. 2. MOS model • BSIM3v3 Berkeley New BSIM4 • MOS Model 9 « MM9 » (ST, Philips) Soon stopped 20 Basic parameters 60 secondary parameters 120 fitting parameters

10. 2. MOS model BSIM4 threshold model Berkeley Vth (V) Short channel effects Channel length (µm)

11. 2. MOS model BSIM4 threshold model Berkeley Ids Ids (Log) Vgs (V) Vds (V)

12. Poor fit Good fit The MOS model is reliable within its optimized range 2. MOS model Width (µm) 100.0 Reference Output pad 10.0 Length (µm) 1.0 0.0 5.0 7.5 10 2.5

13. Achieve good fit with static measurements using a wide set of tricks and internal arrangements 2. MOS model • Around 200 parameters • Model gourous • Model is becoming a service

14. 2. MOS model Layout W=100µm L=0.25µm in a square area?

15. VSS 3D view 2. MOS model Shielded MOS, for mixed signal applications 2D view

16. Total Fringing effects are comparable to area 3. Interconnect Model C (F/m)= e0er w/h e0=8.85e-12 F/m Capacitance w=1µm e=1µm w Capacitance(aF/µm) e 1000 h 100 Plane 10 0.01 0.1 1.0

17. 3. Interconnect Model Formulation in CAD tools based on 2D solvers Sakurai formulas Delorme formulas Page C11= 0.r *(1,13*w/h+1.443(w/h)^0,11+1.475 (t/h)^0.425)

18. 3. Interconnect Model Resistance

19. 3. Interconnect Model Simple line model Very short interconnect Medium interconnect Long interconnect No precise info in DRM, still research

20. 3. Interconnect Model Measurement/Simulations 5mm Voltage Near end Far end Time (ns) CRC model fits well in 0.25µm (hcmos7)

21. Volt 2 3 5 4 1.5 2 3 1 2 1 0.5 1 0 0 0 0 0.5 1.0 1.5ns 0 1 2 3ns 0 0.25 0.5 0.75 1.0ns 3. Interconnect Model Volt Volt 0.35 µm 0.18µm 0.7 µm Cu Al Al Repeaters help to propagate signals at long distance 3Rx3C=9RC (680ps) 3mm 3RC+2tgate (380ps) 1mm 1mm 1mm

22. 3. Interconnect Model Technology 0.70µm Gate delay 0.50µm Aluminium 0.35µm 0.25µm 0.18µm Copper 0.12µm 0 500 1000 1500 Gate delay (ps)

23. 4. Crosstalk Effects Rising importance of coupling capacitance 0.7 µm 0.18 µm New parameters in DRM

24. 4. Crosstalk Effects Critical routing length 0.25µm 0.18µm Crosstak (V) 4000µm 2200µm Length (µm)

25. 4. Crosstalk Effects Coupled line model Short coupled interconnects Long coupled interconnects Used for investigating crosstalk

26. 4. Crosstalk Effects Generation Alu SiO2 0.70µm Probable Fault Fault 0.50µm 0.35µm 0.25µm Cu Low K 0.18µm Noise/VDD (%) 0.12µm 0 25% 50% 75% 100% Crosstalk is a major signal integrity challenge

27. Conclusion • Specific technological options described • Complex MOS models are mandatory • BSIM3v3, soon BSIM4 • Interconnect is the main delay limiting factor • A C/R/C model is accurate for simulating signal transport • Crosstalk is a major signal integrity challenge