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CRU PCIe usage

CRU PCIe usage. DMA engine. firmware. sofware. start_add #0. start_add #2. super page #0. super page #2. DMA engine. start_add #31. super page #1. super page #31. start_add #1. DMA engine. firmware. sofware. start_add #0. start_add #2. super page #0. super page #2.

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CRU PCIe usage

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  1. CRU PCIe usage

  2. DMA engine firmware sofware start_add #0 start_add #2 super page #0 super page #2 DMA engine start_add #31 super page #1 super page #31 start_add #1

  3. DMA engine firmware sofware start_add #0 start_add #2 super page #0 super page #2 DMA engine start_add #31 super page #1 super page #31 start_add #1 START ADD | SIZE

  4. DMA engine firmware sofware start_add #0 start_add #2 super page #0 super page #2 DMA engine start_add #31 super page #1 super page #31 start_add #1 START ADD | SIZE START ADD | SIZE

  5. DMA engine firmware sofware start_add #0 start_add #2 super page #0 super page #2 DMA engine start_add #31 super page #1 super page #31 start_add #1 START ADD | SIZE START ADD | SIZE START ADD | SIZE

  6. DMA engine firmware sofware start_add #0 start_add #2 super page #0 super page #2 DMA engine start_add #31 super page #1 super page #31 start_add #1 START ADD | SIZE START ADD | SIZE START ADD | SIZE

  7. SUPER PAGE 8 KB page • SUPER PAGE feature • multiple of 32 KB (firmware requirements) • super page is contiguous in memory (all the pages have consecutive addresses) • every page in the superpage is 8KB (firmware requirements) 8 KB page

  8. PERFORMANCE

  9. DATA FLOW 32 KB ON CHIP MEMORY USER DATA DMA engine DATA TO HOST MEMORY

  10. PCIe usage DMA acknowledge (data has been moved in the host memory) DATA

  11. PCIe usage DMA acknowledge (data has been moved in the host memory) DATA

  12. PCIe usage DMA acknowledge (data has been moved in the host memory) DATA In this situation the firmware has to wait 1 acknowledgment from the DMA engine before overwriting the data in the memory

  13. PCIe usage DMA acknowledge (data has been moved in the host memory) DATA

  14. PCIe usage • Understanding the counters • there are 2 components in the DMA that control the data throughput: • DATA FLOW CONTROLLER : write the DATA in the ONCHIP MEMORY • DESCRIPTOR CONTROLLER : triggers the DMA engine to move the DATA into the host memory • we have 2 different counters in the firmware: • counts how many clock cycle we wait for at least 1 acknowledge from the DMA (how fast we can write) • counts the number of clock cycle between 2 DMA descriptors (how fast we can read)

  15. Time between 2 DMA DESCRIPTORs The readout of the value was taken every 1s over a long run (~1h) 1 CC = 4 ns MEAN VALUE 292 cc = 1.168 us MAX VALUE 2639 cc = ~10 us

  16. Time spent waiting for DMA ACK signal The readout of the value was taken every 1s over a long run (~1h) 1 CC = 4 ns MEAN VALUE 37 cc = 148 ns MAX VALUE 2342 cc = ~9 us

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