1 / 45

HardWire TM Products: FPGA cost reduction made simple

HardWire TM Products: FPGA cost reduction made simple. ASIC SOFTWARE TOOL METHODOLOGY. FPGA. HardWire. CORES. Objectives. At the conclusion of the presentation attendees should understand the following: HardWire definition and mission FPGA/HardWire relationship

whitby
Download Presentation

HardWire TM Products: FPGA cost reduction made simple

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. HardWireTM Products:FPGA cost reduction made simple ASIC SOFTWARE TOOL METHODOLOGY FPGA HardWire CORES

  2. Objectives At the conclusion of the presentation attendees should understand the following: • HardWire definition and mission • FPGA/HardWire relationship • HardWire value to customers • FPGA and ASIC vendors competitive offerings • Basic selling strategy

  3. Defining HardWire • Products • Three generations of technology leadership • History • Success in the market • Philosophy • The mission of HardWire • Service • Focus on customer satisfaction

  4. HardWire Definition HardWire products are silicon and software products developed with four goals • Provide FPGA emulation using ASIC technology • Use turnkey development based on FPGA design database • Offer FPGA cost reduction • Provide resource reduction vs traditional ASIC re-design

  5. HardWire Conversion The Xilinx Advantage“Design-Once” HardWire ASIC FPGADesign HardWire • Fast Development • Time-to-Market • Concurrent Engineering • Flexibility • No Customer Re-design • No Customer Vectors • FPGA Features • Significant cost reduction Fastest Time from Design Concept to Low-cost Silicon

  6. HardWire Methodology“Design Once” Xilinx HardWire Methodology Typical ASIC Design Phases Capture T e s t D e v e l o p m e n t I t e r a t i o n s Verification FPGA Design Gate Array Redesign Path Place and Route Xilinx ATP Verification Physical Data Base Conversion Physical Data Base Prototypes Production Ready Prototypes

  7. HardWire Technology Roadmap FPGA transition product HW focus on Virtex

  8. Xilinx Has Seven Years of FPGA Conversion Experience with HardWire • Over 800 Xilinx FPGA’s Converted • Over 6 Million Devices Shipped • >90% first-time-right Prototypes • Experience with Complex Designs • PCI, RAM, Configuration emulation (CE), JTAG

  9. HardWire Mission • Extend FPGA Leadership • Provide Customers with a Cost Effective Logic Solution That is superior to traditional ASICs • a. reduced customer resource b. reduced customer risk by linking to Xilinx FPGAs c. reduced “Time-to-Volume” production

  10. HardWire is Organized for Customer Support

  11. The FPGA/ HardWire relationship • Xilinx Strategy • Lead the industry with features,density and cost • HardWire is Key • 4K FPGAs + HW bridge the ASIC gap • The FPGA/ ASIC battle • Design once, sell twice • Customer Product Lifecycles • Good intentions vs reality

  12. Xilinx Product Focus

  13. Market Strategy: Strategic FPGA Support • Strategically support XC4KE/EX/XL FPGA cost reduction requirements • Win higher volume FPGA opportunities • Lessen ASIC competitive threat to FPGA sales • Use as “strategic differentiator” vs. FPGA vendors • Create incremental revenue at target accounts

  14. Product Strategy: FPGA Emulation • Emulate the FPGA using ASIC technology • Support all FPGA features possible per family • Provide substantial price reduction over FPGA • Reduce Customer Re-Design Requirements • Create Customer Time-To-Volume Advantage • Provide a Viable Alternative to ASIC Development

  15. Sales Strategy: Sales and Service Tool • This product is a strategic sales tool • Defense: protect existing sockets • Offense: lock down cost sensitive wins • Offer as a “service” where appropriate • Position capabilities and limitations • Differentiate from ASIC design or FPGA netlist “re-design” • Distinguish “FPGA cost reduction” from “ASIC price competitor”

  16. Use HardWire to Support XC4XL/A:Density and volume are keys (XC4085XL/A) (XC4036XL/A) XC4KXL /A + HardWire Sweet Spot XC4KXL/A + HardWire strategic Density (XC4020XL/A) XC4KXL/A XC4KXL/A+ HardWire Opportunistic 1KU 1000K 10KU Volume 100KU

  17. HardWire Product Roadmap FPGA transition product HW focus on Virtex * 1st Production submittals

  18. Xilinx FPGA + HardWire Advantage“Design Once” Unique Xilinx Logic Methodology Logic Design FPGA “Make” Non-Turn-key “Buy” Turn-Key HardWire ASIC

  19. Typical Product Life Cycle Model • Design and prototype with FPGA • Production ramp in FPGA during HW conversion • FPGA for production upsides and system E-O-L UNPLANNED UPSIDE PROGRAMMABLE VOLUME PRODUCTION RAMP-UP VOLUME END-OF-LIFE HardWire Device

  20. Customer’s Plan is Different • Most customers use the model below • The problem with this model is: • Always redesign • Production never ramps this fast! PRODUCTION RAMP IN ASIC OR HARDWIRE END-OF-LIFE HardWire Device FPGA PROTOTYPE

  21. Real Product Life CycleThe Value of FPGA + HardWire • Redesign flexibility with FPGA • Initial production with FPGA • Convert to HardWire when code is stable UNPLANNED UPSIDE VOLUME PRODUCTION RAMP WITH FPGA END-OF-LIFE HardWire Device REDESIGN WITH OFF-THE SHELF FPGA PROTOTYPE & SYSTEM VERIFICATION PRODUCT FAILS

  22. HardWire’s Value to Customers • HardWire’s value proposition • There’s more to value than just product cost • The methodology • DesignLock: The key to HardWire • The technology • Drop-in replacement for FPGAs • Leveling the field vs ASICs • Differentiating HardWire vs ASICs

  23. HardWire Value Proposition

  24. Xilinx Holds the Patent on FPGA Conversion Without Re-Design

  25. DesignLocktm Mapping Preserves CLB Relative Position HardWire Device FPGA CLB Placement Preserved ASIC ASIC Place and Route Algorithms Use Best Random Case for Overall Fit

  26. DesignLocktm Minimizes Routing Change DesignLocktm Preserves Routing and Relative Timing FPGA Device Routing Generic ASIC Routing Can Change Critical Paths

  27. DesignLocktm Reduces Customer Resources

  28. In an ASIC Conversion The Customer Does the Work DesignEntry Netlist Translation to ASIC Library As Needed: Problem solving Logic re-design, verification, simulation Test Prototypes Fix Logic Errors Place and Route Build Prototypes Fix Timing Errors Timing Simulation Write Test Vectors Design Verification Build Production Units Customer ASIC Vendor

  29. Review final conversion report Generate final conversion report Review preliminary conversion report Design Entry CE Integration Test Prototypes Place and Route Simulation LVS/ DRC Scan logic insertion RAM Integration JTAG Integration Build Prototypes Design Conversion Build Production Units HardWire Product Development is Turnkey We do the work so the customer doesn’t have to Customer Xilinx Customer reviews reports and tests prototypes. Conversion work and test development done by Xilinx. Conversion to a generic ASIC requires more work by the customer.

  30. FPGA Features Built Into XH3/L FPGA Features VREF, CLKS POR, CE FpgASIC I/O Uses FPGA JTAG: No change to test program Core FPGA Cores Efficient Hi-Performance ASIC Core PAD FPGA I/O (Driver, ESD, 5V Tolerant) Core OSC

  31. HardWire Differentiation versus ASIC

  32. Competition: Imitation is the greatest form of flattery • FPGA vendors • Altera MPLD: Convert only if we have to • Lucent: MACO is O.K., but you really want an ASIC • ASIC vendors • AMI: Jack of all conversions master of none • Orbit: If at first you don’t succeed, lower the price • Temic: Are we back in the conversion business? • NEC,Toshiba,etc.: FPGA conversion worth the effort?

  33. HardWire Competition: Altera • MPLD becoming a focus product line • Minimal resources currently dedicated • Focussed on Max 8K and 10K designs • Strategic opportunities only • Lower FPGA price to compete with HardWire

  34. HardWire Competition: Lucent MACO • HardWire’s #1 customer • Limited internal customer focus • Resources dominated by ASIC business request • Move major accounts to ASIC products • Customer resource intensive conversion • Orca + ASIC vs Xilinx FPGA+HardWire

  35. HardWire Competition: Atmel • Focus on ASIC business • Use limited PLD offerings+ASIC to compete • Limited success converting Xilinx features • Focus on lower density conversions • Aggressive pricing to hide limitations

  36. HardWire Competition: AMI • FPGA conversions to grow ASIC business • Aggressive pricing • Questionable ability to convert FPGA features • Customer services including N:1 • Positions fast TAT and no charge for re-spins • Excess fab capacity for 5v conversions • Limited experience with 3.3v conversions

  37. HardWire Competition: Orbit • Leads with price • Selectively takes $0 NRE deals • Limited success implementing FPGA features • .5m fab for sale • 3.3v capability through fab partners • Xilinx support removed from product literature

  38. HardWire Competition: ASIC Vendors-NEC,Toshiba,IBM,etc. • Focus is ASIC business • 4KE/EX/XL conversions are resource drain • Fixed pin-outs may differ from FPGA pin-out • FPGA features difficult to emulate • Test vectors required • Customer must re-verify converted design • Xilinx assumes risk and responsibility, ASIC vendors assign risk to customer

  39. Future of Competitive Offerings • FPGA vendors • Lucent-Continue to support MACO for opportunistic business. Strategic accounts serviced by ASIC • Altera-APEX, conversion competition forcing end of MPLD. Appearance of product line may remain. • ASIC vendors • AMI/Orbit/Temic: New FPGA architectures difficult to convert. Focus on ASIC only business. Orbit business in jeopardy • NEC,Toshiba,Hitachi:Focus will remain on ASIC only opportunities. Virtex features too difficult to emulate in traditional ASIC architectures.

  40. Keys to Success Selling FPGA+HardWire • Leverage FPGA • Lead with strength of FPGA products • Good Discovery • Information is key to our success • Proper Positioning • Focus on the right opportunities • Customer Support • Good communication simplifies the process

  41. Lead Sales Efforts with Strength of FPGA • Sell benefits of FPGA products first • Flexibility,ease of design,design verification • Time to volume is critical to customers • FPGA features and cores are barriers to ASICs • FPGA process migration leads to cost reduction • HardWire is here to support FPGA sales

  42. Good Discovery Information:Keep the competition honest • Competitive factors • FPGA vendor, ASIC, conversion house • Design specifics • Features, package, schedules • Decision influences • Cost, resources, risk, time to market • Production forecast • Verification in FPGA, production start

  43. Positioning HardWire Sets Expectations • HardWire is valuable to Xilinx customers • Conversion success is our #1 goal • Significant FPGA cost reduction is our target • FPGA +HardWire reduces time to volume • Density focus on 4KE/EX/XL • Volume focus on opportunities >10KU

  44. Customer Support Leads to Satisfaction • Communication is key to a successful conversion • Milestone communication • Design functionality verification before submittal • Review of design center reports with customer • Design/ feature implementation review prior to conversion, conversion report review and sign-off • Follow-up on action items

  45. Key Messages for HardWire High density/ high volume 4KXL FPGA opportunities Reduced conversion risk through DesignLockTM HardWire products: FPGA cost reduction made simple Turnkey conversion: Minimal customer interface Competitive sales tool versus FPGA competition

More Related