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Hardware-Software Codesign. M. Balakrishnan Deptt. of Comp. Sci. & Engg. I.I.T. Delhi. What is Design ?. Synthesis Transforming functional requirements to structural design Validation Simulation to show functional requirements captured using test inputs are met
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Hardware-Software Codesign M. Balakrishnan Deptt. of Comp. Sci. & Engg. I.I.T. Delhi SLD Workshop
What is Design ? • Synthesis • Transforming functional requirements to structural design • Validation • Simulation to show functional requirements captured using test inputs are met • Verification to show equivalence between two design descriptions SLD Workshop
Synthesis • Logic synthesis • FSM synthesis • RTL synthesis • Behavioral synthesis • System synthesis Codesign SLD Workshop
Validation • Simulation • Various levels of abstraction (also resolution) • Formal verification • Proving equivalence between specification and implementation • Mixed approaches • Symbolic simulation SLD Workshop
Why Hardware-Software Codesign? Due to the Changing Design Space SLD Workshop
70’s Design Space Shift and Add Multiplier + Example: y <= c * x ; SLD Workshop
Example : y <= c * x ; 80’s Design Space Array Combinational Multiplier * SLD Workshop
Example : y <= c * x ; 90’s Design Space Cost? Power? Performance? Value of c? Encoding of c? Shift and Add Multiplier Array Combinational Multiplier Array Combinational Multiplier + * SLD Workshop
Shift and Add Multiplier Array Combinational Multiplier + * Example : y <= c * x ; Today’s Design Space Cost? Power? Performance? Value of c? Encoding of c? Source and destination of x & y? Frequency of execution ? HW SW RISC DSP VLIW SLD Workshop
Heterogeneity of Platforms Apart from the need to explore the vast design space, heterogeneity of the modern SoC platforms pose a major co-design challenge • Hardware resources • Software programmable resources • Reconfigurable resources SLD Workshop
Co-design Environment • Unified representation of design as well as test benches • Codesign • Co-synthesis • Co-verification SLD Workshop
Unified Representation • C/C++ • MATLAB • SpecC • SystemC/SystemVerilog This also act as co-simulation platforms and are driven by a library with models of both hardware and software components SLD Workshop
Hardware-Software Co-Synthesis: Key Issues • Partitioning • Estimation (area, power, performance) • Communication models • Real-time scheduling issues • HW Synthesis • IP reuse • SW Synthesis • ASIPs and Retargetable code generation SLD Workshop
Granularity • Operation level • Basic block level • Function level • Process/task level SLD Workshop
Partitioning Granularity Process p1; … Function f1 … A := B op C; x := y op z; … Process p2; … Process p3; … SLD Workshop
Partitioning Granularity Process p1; … Function f1 … A := B op C; x := y op z; … Process p2; … Process p3; … Candidate 1: operation Candidate 2: operation SLD Workshop
Partitioning Granularity Process p1; … Function f1 … A := B op C; x := y op z; … Process p2; … Process p3; … Candidate: basic block SLD Workshop
Partitioning Granularity Process p1; … Function f1 … A := B op C; x := y op z; … Process p2; … Process p3; … Candidate: function SLD Workshop
Partitioning Granularity Process p1; … Function f1 … A := B op C; x := y op z; … Process p2; … Process p3; … Candidate 1: process p1 Candidate 2: process p2 Candidate 3: process p3 SLD Workshop
Partitioning Granularity The main consideration to decide on the granularity of partitioning is the coupling between hardware and software This translates to • Latency for data transfer • Transfer rate • Synchronization overheads SLD Workshop
Coupling Example: Close www.stretchinc.com SLD Workshop
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Coupling Example: Loose Network SLD Workshop
Synthesis Example SLD Workshop
Performance Estimation Complexity due to shared resources • Bus • Memory CPU Mem. ASIC 1 ASIC 2 SLD Workshop
Communication Estimation • Interconnection structures • Shared bus • Cross bar or other switches • Data transfer modes • Word transfer • DMA transfer • Inter-connection overheads • Resource contention and prediction SLD Workshop
Hardware Synthesis • Data transfers and data sharing • Type conversions • C to HDL • RTL Synthesis Key challenge is to use existing designs and make them compatible SLD Workshop
Software Synthesis • Real-time scheduling kernel • I/O Drivers and interfacing • ASIPs and application specific FUs • Retargetable code generation SLD Workshop
Thank You SLD Workshop