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Chapter 9

Chapter 9. Counters. Asynchronous Counter Operation. Figure 9--1 A 2-bit asynchronous binary counter. . Figure 9--2 Timing diagram for the counter of Figure 9-1. As in previous chapters, output waveforms are shown in green.

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Chapter 9

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  1. Chapter 9 Counters

  2. Asynchronous Counter Operation Figure 9--1 A 2-bit asynchronous binary counter.

  3. Figure 9--2 Timing diagram for the counter of Figure 9-1. As in previous chapters, output waveforms are shown in green.

  4. Figure 9--3 Three-bit asynchronous binary counter and its timing diagram for one cycle.

  5. Figure 9--4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.

  6. Figure 9--5 Four-bit asynchronous binary counter and its timing diagram.

  7. Figure 9--6 An asynchronously clocked decade counter with asynchronous recycling.

  8. Figure 9--7 Asynchronously clocked modulus-12 counter with asynchronous recycling.

  9. Figure 9--8 The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)

  10. Figure 9--9 Two configurations of the 74LS93A asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.)

  11. Figure 9--10 74LS93A connected as a modulus-12 counter.

  12. Synchronous Counter Operation Figure 9--11 A 2-bit synchronous binary counter.

  13. Figure 9--12 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal).

  14. Figure 9--13 Timing diagram for the counter of Figure 9-11.

  15. Figure 9--14 A 3-bit synchronous binary counter.

  16. Figure 9--15 Timing diagram for the counter of Figure 9-14.

  17. Figure 9--16 A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas.

  18. Figure 9--17 A synchronous BCD decade counter.

  19. Figure 9--18 Timing diagram for the BCD decade counter (Q0 is the LSB).

  20. Up/Down Synchronous Counter

  21. Figure 9--23 A basic 3-bit up/down synchronous counter.

  22. Figure 9—24 : Example 9-4 - Timing Diagram

  23. Design of Synchronous Counters Figure 9--27 General clocked sequential circuit.

  24. Step 1: State Diagram Figure 9--28 State diagram for a 3-bit Gray code counter.

  25. Step 2: Next-State Table

  26. Step 3: Flip-Flop Transition Table

  27. Step 4: Karnaugh Maps Figure 9--29 Examples of the mapping procedure for the counter sequence represented in Table 9-7 and Table 9-8.

  28. Step 5: Logic Expressions for Flip-Flop Inputs Figure 9--30 Karnaugh maps for present-state J and K inputs.

  29. Step 6: Counter Implementation Figure 9--31 Three-bit Gray code counter.

  30. Figure 9—32 : Example 9-5

  31. Figure 9--33

  32. Figure 9--34

  33. Figure 9--35 Example 9-6 - State diagram for a 3-bit up/down Gray code counter.

  34. Figure 9--36J and K maps for Table 9-11. The UP/DOWN control input, Y, is treated as a fourth variable.

  35. Figure 9--37 Three-bit up/down Gray code counter.

  36. Cascaded Counters Figure 9--38 Two cascaded counters (all J and K inputs are HIGH).

  37. Figure 9--39 Timing diagram for the cascaded counter configuration of Figure 9-38.

  38. Figure 9--40 A modulus-100 counter using two cascaded decade counters.

  39. Figure 9--41 Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-10 and divide-by-100 outputs.

  40. Figure 9—42 : Example 9-7 – Determine the overall modulus

  41. Figure 9--43 A divide-by-100 counter using two 74LS160 decade counters.

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