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Microprocessor system architectures – IA32 paging

Microprocessor system architectures – IA32 paging. Jakub Yaghob. Control – global setting. Paging modes. Address translation – 4K pages , 32-bit physical address. Address translation – 4 M pages , 32-bit physical address. Page Directory – 4K/32b. Page Table – 4K/32b.

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Microprocessor system architectures – IA32 paging

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  1. Microprocessor system architectures – IA32 paging Jakub Yaghob

  2. Control – global setting

  3. Paging modes

  4. Address translation – 4K pages, 32-bit physical address

  5. Address translation – 4Mpages, 32-bit physical address

  6. Page Directory – 4K/32b

  7. Page Table – 4K/32b

  8. Page Directory – 4M/32b

  9. PAE – Page Address Extension • Widens possibility of addressing physical memory to 36 bits (64GB) • Available from Pentium Pro • Paging data structures changed • Other release of OS (different compilation) • PDBR changed • Bit NX (No eXecute)/XD (eXecution Disabled) • NewerAMD/Pentium 4

  10. Address translation – 4K pages, 36-bit physical address

  11. Address translation – 2Mpages, 36-bit physical address

  12. Page table entries – 4K/36b

  13. Page table entries – 2M/36b

  14. PSE-36 – Page Size Extension 36-bit • An alternate method to the PAE • Allows addressing of 36 bits physical address space using 4M pages • Available fromPentium III • Only whenPSE-36 flag available (CPUID[17])

  15. Address translation – 4Mpages, 36-bit physical address

  16. Page Directory – 4M/36b

  17. Page fault • All paging problems caught by #PF exception • Flag P set to 0 • Access rights violation • Page table or page directory

  18. Protection • U/S flag • =0 – supervisor mode • CPL 0-2 • =1 – user mode • CPL 3 • R/W flag • =0 – read-only • Not used insupervisor mode, until flagWP (CR0[16]) is set • =1 – read/write • NX/XD flag • =0 – can execute • =1 – no execute

  19. TLB – Translation Lookaside Buffer • Associative memory for accelerating translation from linear to physical address • TLB purging • Explicitly usingmovcr3,eax • Implicitly during task change – reading new CR3 • Entries with G flag set are not purged when PGE is set (CR4[7]) • Selective entry purging • InstructionINVLPG

  20. Process-context ID • Cache information for multiple linear-address spaces • 12-bit ID • Enabled by CR4.PCIDE=1 • Bits CR3[11:0] • Bits PCD, PWT treated as 0 • TLB entries widened with PCID • TLB translation only for current PCID

  21. PAE in long mode • Max limits • 64-bit linear address • 52-bit physical address • Current implementation • 48-bit linear address • 40-bit physical address • Setting • PAE must be enabled before switching to long mode

  22. Address translation – 4K pages in long mode

  23. Address translation – 2Mpages in long mode

  24. Page table entries – 4K/long mode – I

  25. Page table entries – 4K/long mode – II

  26. Page table entries – 2M/long mode

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