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Explore the advanced architecture of MIPS/PIC32 processors, including 32-bit RISC technology, multi-segment memory model, and instruction set design. Learn about memory management, kernel mode, and I/O functions in this comprehensive course.
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Embedded Computer – Master 2009 • Curs9 • MIPS/PIC3 – Arhitectura • PIC32 – set instructiuni • MIPS PIC32 – functii I/O • PIC32 – C i/o port • Lab.9 – Intreruperi Timer1 • Extensii NXT
MIPS – Nucleu centarl - Full 32-bit RISC technology - Register-based processor - Five stage pipeline - MIPS16e for improved code density - Virtual addresses with fixed mapping - Multi-segment memory model - User and Kernel Mode
MIPS –Prefech Fetches 128-bit data 4x32-bit instructions 8x16-bit instructions Up to 80 MIPS of linear execution 256 Bytes Cache 16 total lines Up to 4 data lines Lockable Lines
MIPS C32 - Atomic bit manipulation Atomic bit manipulation via special SET, CLR, & INV registers allows faster operations Operates on corresponding base register Only bits specified as ‘1’ are modified Writing 0x0001 to TRISASET register sets only bit 0 in base register TRISA Writing 0x0020 to PORTDCLR register clears only bit 5 in base register PORTD Writing 0x9000 to LATCINV register inverts only bits 15 and 12 in the base register LATC
MIPS C32 – Fisier initializare crt0.o Compiler’s crt0.o performs processor initialization - Initialize Stack, Heap and Global pointers - Clear Uninitialized Data Sections - Copy Initialized Data Flash to Data Memory - Copy RAM Functions from Program Flash to Data Memory - Initialize CP0 Registers - Initialize Exception Vectors - Call main()
