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Rad. Test in ALICE/TOF

Rad. Test in ALICE/TOF. TOF Overview and radiation levels Irradiation at PSI of Tdc Readout Module component candidates (incl. Altera FPGA) Irradiation at Legnaro of HPTDC Error rates Outlook.

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Rad. Test in ALICE/TOF

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  1. Rad. Test in ALICE/TOF • TOF Overview and radiation levels • Irradiation at PSI of Tdc Readout Module component candidates (incl. Altera FPGA) • Irradiation at Legnaro of HPTDC • Error rates • Outlook P. Antonioli on behalf of TOF + A. Mati, M. Pieracci, C. Tintori (CAEN) and many thanks to A. Candelori (SIRAD), H. Wojtek (PSI) and F. Faccio (CERN) P. Antonioli - TOF /INFN-Bologna

  2. TOF overview 18 TOF supermodules Front-End cards with ASIC 8 m Rad-tolerance issues for electronics inside crates Crates with HPTDC P. Antonioli - TOF /INFN-Bologna

  3. Radiation simulation Z axis crate crate 378 -378 Please note: Used for rad. simulation (ALICE-INT-2002-28) 370<R<399 and –378<Z<378 for scoring, but370<R<399 and (–375<Z<-425;375<Z<425) for TOF crates (asked Andreas to introduce devoted scoring for TOF crates in further simulations) P. Antonioli - TOF /INFN-Bologna

  4. Radiation levels Radiation levels expected at ALICE/TOF: 1.2 Gy/10 years (TID) Total neutron fluence (>20 MeV): 1.6 109 /cm2/10 years. Total charged hadrons (>20 MeV): 5.3 108 /cm2/10 years. 89 Hz/cm2 expected in PbPb MB events (hadrons+neutrons > 20 MeV). For ALICE/TOF careful design needed to handle SEU, Degradation for TID effects neglectable. Latchup protections needed. P. Antonioli - TOF /INFN-Bologna

  5. TRM conceptual design HPTDC HPTDC INPUTS (LVDS) INPUTS (LVDS) SRAM 32 SRAM 684 Tdc Readout Module inside crates HPTDC LUT FIRMWARE SRAM FLASH HPTDC LUT TRG ReadoutController BOOT 32 mC SEL WATCHDOG x 15 L1 VMEInterface Output Fifo TRG 32 32 32 x 15 VME bus 32 L2a EventManager L2r Tested all components during 2004 irradiationcampaigns 32 EVENT BUFFERS Functionalities implemented by an FPGA P. Antonioli - TOF /INFN-Bologna

  6. Radiation tolerance test Test at PSI (Zurich) June 2004 Test card for all (except HPTDC) componentsforeseen for TRM (Altera Stratix EP1S20F780, IDT Ram, Atmel Flash and Micro) and latchup/SEU error recovery strategy • Results: • all memories, mC, voltage regulator validated • SEU rate in Altera Stratix (obtained by means of Altera CRC_ERROR built-in feature) too high (we will move to Actel ProAsic Plus) P. Antonioli - TOF /INFN-Bologna

  7. Radiation tolerance board Altera Stratix (and Cyclone) feature: real-time monitoring of configuration bits: a clear procedure to establish configuration changed (effective SEFI monitor) Atmel mC acts as controller of power fault (latchups) + CRC_ERROR pin FLASH AT45DB161B 16 Mb VCC FIRMW. A FIRMW. B Monitor of errors in SRAM, FPGA internal memory + shift register logic check P. Antonioli - TOF /INFN-Bologna

  8. Stratix results ALTERA STRATIX EP1S20 (configuration upset) Used two indipendent methods to estimate cross sections s = (6.5± 0.2 (stat)) 10-8 cm2 Reasonably consistent with existing results for 0.13 CMOS SRAM (Anelli et al. @RADECS 2003) O(s) 10-14 cm2/bit metallic package + Coulombian barrier P. Antonioli - TOF /INFN-Bologna

  9. SRAM and other... No latchup observed. TID = 14 krad. P. Antonioli - TOF /INFN-Bologna

  10. HPTDC irradiation at Legnaro SIRAD facility devoted to irradiation with heavy ions (ions available for 1 MeVcm2/mg<LET < 80 MeVcm2/mg) at INFL Legnaro Labs. 20520 HPTDC to be deployed on ALICE/TOF. CMS measurement on HPTDC:(8 HPTDC irradiated with 5 1010 protons/cm2 @ 60 MeV, no SEL detected, just 1 SEU): Extrapolation to TOF: MTBF 2.4 days in the whole detector Measurement with heavy ions to check previous measurement and characterize SEU cross sections of internal registers and memories as a function of LET P. Antonioli - TOF /INFN-Bologna

  11. HPTDC test board Read-out via JTAG interface Upset monitoring via JTAG (built-in feature of HPTDC) 687 bits of configuration 40 Kb of internal memory Latchup monitor Decapsulation needed P. Antonioli - TOF /INFN-Bologna

  12. HPTDC irradiation results s = 2.4 10-14 cm2/bit s = 3.8 10-15 cm2/bit s = 6.7 10-15 cm2/bit Weibull fits + conversion to a cross-section for 60 MeV proton irradiation (M. Huthinen and F. Faccio, NIMA450, 155(2000)) s = 3. 10-12 cm2 Contribution from state machine errors P. Antonioli - TOF /INFN-Bologna

  13. Error rates at ALICE/TOF 100 Hz Current simulation: 89 Hz (possible geometrical overestimation 30%) board (nd= 1), crate (nd= 10) TOF (nd=684) Er (h-1) = f (part/cm2/s) s (cm2) 3600 (s/h) nd MTBF: Minimum Time Between Failure = 1 / Er P. Antonioli - TOF /INFN-Bologna

  14. SEU Error rates for TRM (1) MTBF (min) 3.8 14.3 2300 • MTBF for Stratix too small, moving to Actel • HPTDC LUT will be periodically monitored (CRC) + reload from Flash • Error rates in event buffers depends on L1 rate, L2 latency + TOF occupancy. Error rates here are for L1=1 KHz , 30% TOF occupancy (exp. 15%)). CRC check will be implemented. P. Antonioli - TOF /INFN-Bologna

  15. SEU error rate for TRM (2) MTBF (day) 1.8 800 260 • As expected error rate for configuration dominant • Nice agreement with CMS previous measurement • Error rates for readout fifo and L1 buffers are dependent also on L1 latency, read-out time, TOF occupancy and L1 rate (here assumed 30% occ. + 1KHz for L1) P. Antonioli - TOF /INFN-Bologna

  16. Some general comments SRAM, mC, clock, voltage regulator, Flash and HPTDC: OKFirmware to check SEU for Flash, SRAM (LUT for HPTDC and event buffers) under development. Irradiations with heavy ions of HPTDC gave results in nice agreement with existing data (irradiation with protons). HPTDC error rate ok. The CRC control mechanism in Altera Stratix works very well. Depending on system dimension, radiation level and application, it is a suitable option for LHC applications. Unfortunately this is not the case for ALICE/TOF. Error rate is too high (at least for TRM and DRM). Current best candidate: Actel ProAsic Plus APA600. P. Antonioli - TOF /INFN-Bologna

  17. Outlook We will provide Vpp = 16.2 V and Vpn=-13.5 V in crate backplane (use ± 12V VME lines) to allow remote Actel programming. Porting to Actel under way. For other VME modules (DRM: data readout; LTM trigger) similar design and choice of components (SRAM, FLASH, boot strategy...). Altera still an option for some functionality of LTM. We plan another irradiation campaign (21/22 October @ Louvain) to check slow control solution (PMC PowerPC or ARM to be evaluated, Excalibur as backup [scaling TPC results MTBF: 20 h]. Optical link could be also an option) and some component of LTM. P. Antonioli - TOF /INFN-Bologna

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