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8253/54 Timer and Music

8253/54 Timer and Music. Section 5.1 8253/54 Timer Description and Initialization PTI (programmable Interval Timer) The 8253 chip was used in the IBM PC/XT, but starting with the IBM PC/AT, the 8254 replaced the 8253. 8253 and 8254 have exactly the same pinout.

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8253/54 Timer and Music

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  1. 8253/54 Timer and Music • Section 5.1 8253/54 Timer Description and Initialization • PTI (programmable Interval Timer) • The 8253 chip was used in the IBM PC/XT, but starting with the IBM PC/AT, the 8254 replaced the 8253. • 8253 and 8254 have exactly the same pinout. • 8254 is a superset of the 8253.

  2. Programmable Interval Timer - 8254

  3. Pin Description of 8253/54 • A0, A1, and CS • Inside the 8253/54 timer, there are 3 counters. • Each timer works independently and programmed separately. • Each counter is assigned an individual port address. • The control register common to all 3 counters and has its own port.

  4. CLK • CLK is the input clock frequency, which can range between 0 and 2 MHz for the 8253. • For input frequencies higher than 2 MHz, the 8254 must be used. • The 8254 can go as high as 8 MHz, and 8254-2 can go 10 MHz. • OUT • Can have square-wave, one-shot, and other square-shape waves for various duty cycles but no sine-wave or saw-tooth shapes. • Gate • This pin is used to enable or disable the counter.

  5. D0-D7 • The D0-D7 data bus of the 8253/54 is a bidirectional bus connected to D0-D7 of the system data bus. • RD and WR are connected to IOR and IOW control signals of the system bus. • Initialization of the 8253/54 • Each of the three counters of the 8253/54 must be programmed separately. • The 8253/54 must be initialized before it is used.

  6. Control word • The figure shows the one-byte control word of the 8253/54. • D0 chooses between a binary number divisor of 0000 to FFFFH or a BCD divisor of 0000 to 9999H. • The highest number is 216 for binary and 104 for BCD. • To get the highest count, the counter is loaded with zeros. • D1, D2, and D3 are for mode selection.

  7. D4 and D5 are for RL0 and RL1 • RL0 and RL1 are used to indicate the size of the divisor, and have 3 options: • Read/write MSB only • Read/write LSB only • Read/write LSB first followed immediately by the MSB.

  8. Operation Modes Mode 0 Interrupt on terminal count Mode 1 Programmable one-shot Mode 2 Rate Generator Mode 3 Square wave rate generator Mode 4 Software triggered strobe Mode 5 Hardware trigger strobe

  9. All counters are down counters. • D6 and D7 are used to select the 3 counters, counter 0, counter 1, or counter 2, is to be initialized by the control byte. • To program a given counter of the 8253/54 to divide the CLK input frequency one must send the divisor to that specific counter’s reg. • To divide the frequency by 10000 (BCD) or 65536 (binary) we must send in 0 for both high and low bytes.

  10. Section 5.2 IBM PC 8253/54 Timer Connections and Programming

  11. The three clocks of the 8253, CLK0, CLK1, and CLK2, are all connected to a constant frequency of 1.1931817 MHz. • PCLK of the 8284 is 2.3863663 mhZ and must be divided by 2. • GATE0 and GATE1 enable counter0 and counter 1 respectively. • GATE2 of counter 2 can be enabled or disabled through PB0 of port B of the 8255.

  12. Using counter 0 • CLK0 of counter 0 is 1.193 MHz, and GATE0 is connected permanently. • OUT0 is connected to IRQ0 of the 8259 interrupt controller to provide time-of-day (TOD) interrupt. • IRQ0 is activated 18.2 times per second. (18.2 Hz) • The counter must to divide 1.193 MHz by 65,536.

  13. Using counter 0 • The wave shape is a square wave. • D0 = 0 for the binary value. • D3 D2 D1 = 011, mode 3 • D4 D5 = 11, for reading/writing the LSB first, followed by MSB. • D7 D6 = 00, for counter 0.

  14. Using counter 0 • The function of IR0 is not only taking care of the TOD clock. • BIOS will make this interrupt available by going to the vector table of INT 1CH.

  15. Using Counter 1 • In counter 1, CLK1 is connected to 1.193 MHz and GATE is high. • OUT1 generates a periodic pulse required to refresh DRAM memory of the computer. • The refreshing must be done at least 15s (66278Hz) for each cell, and is performed by DMA. • Counter must divide the input frequency 1.19318 MHz by 18. • DRAM maximum frequency refresh time is 2 ms.

  16. Using Counter 1 D0 = 0 for binary option D3 D2 D1 = 010, for mode 2 shape output. D5 D4 = 01, for LSB only D7 D6, for counter 1. D7~D0 = 0101 0100 = 54H for the control word.

  17. Using Counter 2 • The output of counter 2 is connected to two different devices: the speaker and PC5 of the 8255. • Use of timer 2 by the speaker • In the IBM PC, CLK2 is connected to a frequency of 1.19318 MHz and GATE2 is programmed by PB0 of port 61H (port B). • The IBM PC uses counter 2 to generate the beep sound. • The beep sound has a frequency of 896 Hz (divisor = 1331)

  18. Turning on the speaker via PB0 and PB1 of port 61H • The process of turning on the speaker is the same for all IBM PCs and compatibles from 8088-based to 80486 and Intel’s Pentium-based systems. • Gate2 must be high to provide the CLK to timer 2. • This function is performed by PB0 of port 61H. • The following is the code to turn the speaker on.

  19. Turning on the speaker via PB0 and PB1 of port 61H

  20. Time delay for 80x86 PCs • Creating time delays in 8088/86-based PC/XT, PS2, and compatibles • MOV CX, N • AGAIN: LOOP AGAIN • The above codes can be used to generate delays (N  T 17 seconds) • Approximate delay time • The delay is not only frequency dependent but also CPU dependent. • IBM provides a scheme to create a time delay using hardware that is not only frequency but also CPU independent.

  21. Time delays in 80x86 IBM PC • The following method of creating hardware time delays was first implemented in the IBM PC and compatible computers. • To create a processor independent delay, IBM made PB4 of port 61H toggle every 15.085s. • CS holds 15.085s in the following codes.

  22. Time delays in 80x86 IBM PC

  23. Time delays in 80x86 IBM PC • Now a time delay of any duration can be created regardless of the CPU frequency as long as it is a 286 and higher PC. • For example set CX=33144 (3314415.085s=0.5 second) • MOV CX, 33144 • CALL WAITF

  24. Time delays in 80x86 IBM PC

  25. Example5-11

  26. Example5-12,5-13,5-14

  27. Generating Music on the IBM PC • As mentioned earlier, counter 2 is connected to the speaker and it can be programmed to output any frequency that is desired. • Look at the list of piano notes and their frequencies given in Fig. 5-5. • Music: frequency and time duration

  28. A delay of 250 ms

  29. Shape of 8253/54 Outputs

  30. Out0 pulse shape in IBM BIOS • IBM BIOS programmed counter 0 to create mode 3, which is square-wave shape. • Counter 0 is loaded with the number 65,536 and the clock period of input frequency 838 ns (1/1.193 MHz = 838 ns), so the period of the OUT0 pulse is equal to 65536838 ns = 54.9 ms (18.2 Hz). • OUT0 continuously sends out square wave pulses.

  31. Out1 pulse shape in the IBM BIOS • IBM BIOS programmed counter 1 in mode 2, rate generator, with the value 18 loaded into the counter. • OUT1 will be high for a total of 17 838 ns and go low for one pulse of 838 ns • GATE1 is set to 1 permanently

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