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Potentials of R&D for ICT in Cooperation with IPSI Belgrade

Potentials of R&D for ICT in Cooperation with IPSI Belgrade. An Overview of IPSI Belgrade Projects for High-Tech Computer Industry in the USA and EU. This material was developed with financial help of the WUSA fund of Austria. IPSI Belgrade.

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Potentials of R&D for ICT in Cooperation with IPSI Belgrade

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  1. Potentials of R&D for ICT in Cooperation with IPSI Belgrade An Overview of IPSI Belgrade Projects for High-Tech Computer Industry in the USA and EU This material was developed with financial help of the WUSA fund of Austria.

  2. IPSI Belgrade • IPSI Belgrade - Jointly founded by German/USA/Japanese/Serbian capital • Some of those responsible for launching: - Fraunhofer IPSI, Darmstadt, Germany - StorageTek, Colorado, USA - M.I.T. of Tokyo, Japan - Telecom Italia Learning Services, L’Aquila, Italy

  3. Employees and Associates • CEO:Prof. Dr. VeljkoMilutinovic, Fellow of the IEEE,Electrical Engineering, University of Belgrade, Serbia • Senior Consultant:Prof. Dr. Erich Neuhold, Fellow of the IEEE, ResearchStudio, Vienna, Austria • Initial Team:JovicDarko, BabovicZoran, Toskov Ivan, VujovicIvana, VujnovicDamjan, KrunicJelena, MilicBratislav, MilutinovicDarko, NikezicGavro, RadakovicMiroslav, Skundric Nikola, MinicPredrag, StanicSasa, KorolijaNenad, RudanSasa, and Kovacevic Aleksandra.

  4. Selected IPSI Belgrade Services • Workspaces of the Future- Environments for Cooperative Working and Learning- Virtual Information and Knowledge Environments- Mobile Interactive Media- Open Adaptive Information Management Systems- Publication Engineering and Technology- Services on the WWW- Infrastructure for E-Business on the Internet

  5. General Project Structure • Industrial Research: • Phase #1: Survey, and Generation of Embryonic Ideas • Phase #2: Analytic Analysis and Comparison (1+K) • Phase #3: Simulation Analysis and Comparison • Phase #4: Implementation Analysis and Comparison

  6. General Project Structure • Industrial Development: • Phase #1: Product Requirements • Phase #2: Intra Module Coding • Phase #3: Inter Module Integration • Phase #4: Exhaustive Verification

  7. Some Recent Educ Projects • Frankfurt/M, Frankfurt/O, Magdeburg, Berlin, Hagen, Koblenz, Kaiserslautern, Erlangen, TUM, IPSI FhG, Karlsruhe, Ulm, ... • NYU, Purdue, Dartmouth, Hawaii, … • Modena, Ferrara, Siena, Pisa, Salerno, Napoli, … • Tech De Monterrey, Tech De Durango, UNAM, La Salle, … • St. Mary’s, Dalhousie, … • RIT, Skoevde, Karlskrona, Karlstadt, … • Valencia, Barcelona, Madrid, Oviedo, …

  8. Some RecentR&D Projects • WSJ, DJ, Finsoft, Microsoft, NCR, Encore/HP, SUN/StT, Intel, … • Comshare, Zycad, QSI, Virtual, … • TechnologyConnect, BioPop, eT, MainStreetNetworks, … • Salerno, Pisa, Siena, L’Aquila, ... • Ulm, Darmstadt, Berlin, Karlsruhe, …

  9. R&D Methodology • Introduction • Problem Statement • Criticism of Existing Solutions • Proposed Solution • Conditions and Assumptions • Details (1+k) • Mathematical Analysis • Simulation Analysis • Implementation Analysis • Conclusion

  10. Internet Servers

  11. NCR: NextGen PC for E-Business • Cache coherence maintenance: Hardware approach • Cache coherence maintenance: Software approach • Accelerator chip for windowing • Accelerator board for dbase applications • Prefetching on the "silence" for disk cacheing • Accelerator chip for text compression • Accelerator chip for JPEG/MPEG

  12. SMP in Action M P

  13. ENCORE/COMPAQ/HP • Improved RMS for PC, and its prototype • The RM/MC for PC approach, and its analysis • Simulation of selected DSM approaches, and their comparison (RMS, KSR, and SCI) • Search for the optimal RMS inteconnect technology

  14. DSM in Action

  15. Prologue

  16. Epilogue

  17. Cutting the Edge • TopDown Technologies • i860 • Selected microprocessor models • QSI • An ATM router chip • In-memory processing

  18. Response: Industry

  19. Flynn, M. J., Computer Architecture, Jones and Bartlett, USA (96)position 1 (12 citations) Bartee, T. C., Computer Architecture and Logic Design, McGraw-Hill, USA (91)position 1 (2 citations) Tabak, D., RISC Systems (RISC Processor Architecture), Wiley, USA (91)position 1s (6 citations) Stallings, W., Reduced Instruction Set Computers (RISC Architecture), IEEE CS Press, Los Alamitos, California, USA (90)position 1s (3 citations) Heudin, J. C., Panetto, C., RISC Architectures, Chapman-Hall, London, England (92)position 3s (2 citations) van de Goor, A. J., Computer Architecture and Design, Addison Wesley, Reading, Massachusetts, USA (2nd printing, 91)position 4s (3 citations) Tannenbaum, A., Structured Computer Organization (Advanced Computer Architecures), Prentice-Hall, USA (90)position 5s (4 citations) Feldman, J. M., Retter, C. T., Computer Architecture, McGraw-Hill, USA (94)position 7s (2 citations) Stallings, W., Computer Organization and Architecture, Prentice-Hall, USA (96)position 9s (3 citations) Murray, W., Computer and Digital System Architecture, Prentice-Hall, USA (90)position >10s (2 citations) Wilkinson, B., Computer Architecture, Prentice-Hall, USA (91)position >10 (2 citations) Decegama, A., The Technology of Parallel Processing (Parallel Processing Architectures), Prentice-Hall, USA (90)position >10s (2 citations) Baron, R. J., Higbie, L., Computer Architecture, Addison-Wesley, USA (92)position >10s (1 citation) Tabak, D., Advanced Microprocessors (Microcomputer Architecture), McGraw-Hill, USA (95)position >10s (1 citation) Zargham, M. R., Computer Architecture, Prentice-Hall, USA (96)position >10s (1 citation) Hennessy, J. L., Patterson, D. A., Computer Architecture: A Quantitative Approach, Morgan-Kaufmann, USA (96)na (0 citations) Hwang, K., Advanced Computer Architecture, McGraw-Hill, USA (93)na (0 citations) Kain, K., Computer Architecture, Addison-Wesley, USA (95)na (0 citations) Response: Academia

  20. N.B. ERRORS MADE & LESSONS LEARNED

  21. 1

  22. 2

  23. 3

  24. The Split Temporal/Spatial Cache • Veljko Milutinović, Boris Marković*, Milo Tomašević, Aleksandar Milenković, and MarkTremblay** • IFACT • Department of Computer EngineeringSchool of Electrical EngineeringUniversity of BelgradePOB 35-5411120 Beograde, Serbia •  ___________________________________________________________________________ * Boris Marković is with the University of Montenegro, Podgorica, Montenegro ** Mark Tremblay is with the SUN Microsystems, Palo Alto, California, USA

  25. MM RUN.time • C2.temp • COMPILE.time C1.spat • C1.temp PFB SPLIT TEMPORAL/SPATIAL CACHE

  26. The Injection Cache Veljko Milutinović, Aleksandar Milenković, Davor Magdić, and Gad Sheaffer* IFACTDepartment of Computer Engineering School of Electrical Engineering University of Belgrade POB 35-5411120 Beograde, Serbia  ________________________________________________________________________ * Gad Sheaffer is with the Intel Corporation, Beverton, Oregon, USA

  27. PRODUCER IN CONSUMER EARLY LATE C2 t t C1 c P CACHE INJECTION

  28. Integrated Systems

  29. VLSI Detection for Internet/Telephony Interfaces Goran Davidović, Miljan Vuletić, Veljko Milutinović, Tom Chen, and Tom Brunett  * eT

  30. USERS... . . . Superposition/DETECTION Superposition/DETECTION SPECIALIZED INTERNET REMOTE SITE SERVICE PROVIDER HOME/OFFICE/FACTORY AUTOMATION ON THE INTERNET

  31. Browser Acceleration Gvozden Marinković, Dragan Jandrić, Vladimir Ivanović, Veljko Milutinović, and Tom Chen  *MainStreetNetworks

  32. What is the Major Bottleneck?Rendering!

  33. BioPoP Veljko Milutinovic, Vladimir Jovicic, Milan Simic, Bratislav Milic, Milan Savic, Veljko Jovanovic, Stevo Ilic, Djordje Veljkovic, Stojan Omorac, Nebojsa Uskokovic, and Fred Darnell  • isItWorking.com

  34. Testing the Infrastructure for EBI • Phones • Faxes • Email • Web links • Servers • Routers • Software • Statistics • Correlation • Innovation

  35. CNUCEIntegration and Dataminingon Ad-Hoc Networks and the Internet Veljko Milutinović, Luca Simoncini, and Enrico Gregory  *University of Pisa, Santanna, CNUCE

  36. GSM Internet DM Ad-Hoc Ad-Hoc

  37. Infrastructure for Collaboration

  38. Technology Transfer Veljko Milutinović, Wendy Chin, Bob Richardson, and Jerome Friedman  *TechnologyConnect.com

  39. Buyers Sellers Reseller/R&D Manager/ Product Line Manager/ Business Development Manager Product Line Manager/ IP Licensing Manager Products Technologies License Agreement Patents Reseller Agreement Expertise Dev. Contract Consultants Acquisition Merger Business Development Consultant Services Expertise $ 216 B <10 % <1%

  40. SocratenonDistant Web Education Engine Nenad Nikolić, Milan Milićević, Milan Trajković, Dragan Milićev, Veljko Milutinović, and Massimo Desanto  *University of Salerno

  41. Web Browser Client Web pages Internet Web Server &Application SQL Server Application Server Intranet Database Server

  42. SSGRROrganizing Conferences via the Internet Zoran Horvat, Natasa Kukulj, Vlada Stojanovic, Dusan Dingarac, Marjan Mihanovic, Miodrag Stefanovic,Dusan Savic, Bratislav Milic, Zaharije Radivojevic, Ivana Vujovic, and Ivan Toskov, Veljko Milutinovic, and Frederic Patricelli  *SSGRR, L’Aquila

  43. 2000: Arno Penzias 2001: Bob Richardson 2002: Jerry Friedman 2003: Harry Kroto

  44. University of UlmReverse Engineering of GeForce2-4 Sasa Jandric, Zaharije Radivojevic, Milos Cvetanovic, and Veljko Milutinovic 

  45. 010101000001101101 • Developing system control programs (drivers) for GeForce 2-4, for the Plurix operating system • Main advantage of the GeForce chip (called graphical processor) is the use of 3D accelerating functions • Reversed engineering is used as a technology for finding previous information on the GeForce chip

  46. Intelligent Search

  47. Genetic Search with Spatial/Temporal Mutations Jelena Mirković, Dragana Cvetković, and Veljko Milutinović  *Comshare

  48. Drawbacks of INDEX-BASED: Time to index + rankingAdvantages of LINKS-BASED: Mission critical applications + customer tuned ranking Well organized markets: Best first search If elements of disorder: G w DB mutations Chaotic markets:G w S/T mutations Provider

  49. Reconfigurable FPGA for SA Božidar Radunović, Predrag Knežević, Veljko Milutinović, Steve Casselman, and John Schewel*  * Virtual

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