1 / 21

Green Transistor for 10X Lower IC Power ?

This article discusses the need to reduce IC power consumption and introduces the concept of a green transistor that can achieve a 10X lower power consumption. It explores the challenges in reducing power consumption and proposes a solution using a new transistor structure.

wvance
Download Presentation

Green Transistor for 10X Lower IC Power ?

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Green Transistor for 10X Lower IC Power ? Chenming Hu University of California, Berkeley Supported by: DARPA STEEP, FCRP-MSD

  2. the world enabled electronic systems IC chips fabs transistors Electronics Infrastructure $ 6/2009 Chenming Hu

  3. Expectation:ICs will be even more.. • Affordable (size reduction..): manufacturing, device physics limit,… • Useful (speed, density..): natural human interface, bio-medical sensing… • Usable (low power): heat management, portability, global energy conservation… 6/2009 Chenming Hu

  4. Power Consumption Problems • Thermal management/package issues may limit integration density. • IC usage of electricity at an inflection point. • ICs use a few % of world’s electricity today and growing exponentially. • Power per chip is growing. • IC units in use also growing. • Need to reduce IC power consumption with architecture and circuit innovations, and a low voltage transistor. 6/2009 Chenming Hu

  5. IC Power Consumption Rising Much Faster Than Past Trend • Because power consumption Vdd2 • and Vdd (operation voltage) scaling has slowed. High Performance ITRS Roadmap 6/2009 Chenming Hu

  6. Why Vdd scaling slowed • We used to control power by scaling Vdd and maintain good speed by reducing Tox. • But,Tox can not be reduced much more, not even with high-k dielectrics. • But new materials will raise the mobility, μ Speed transistor current μ ( Vdd – Vt ) / Tox 1.2 nm SiO2 6/2009 Chenming Hu

  7. Gate Source Drain 3nm Ge film Oxide Silicon New material, e.g. Ge film on Si substrate Industry is also funding InGaAs, InAs, and graphene MOSFET research. 6/2009 Chenming Hu

  8. How to Reduce Power by 20X • Two steps to reduce Vdd to 0.2V for 20x power reduction? • Reduce Vdd – Vt to < 0.15V with high-mobility-channel material (Ge, III-V, graphene...), etc. • Reduce Vt to 50mV. But, there is the fundamental 60mV/decade turn-off limit ….. 6/2009 Chenming Hu

  9. Ioff Limit - 60mV/decade Swing Source: Intel Corporation m) m Lower Vt -3 (A/ 10 Vt DS -5 10 -7 10 Drain Current, I -9 10 -11 10 Gate Voltage, V (V) 0.0 0.3 0.6 0.9 GS Lowering Vt by 60mV increases the leakage current (power) by 10 times. 9 6/2009 Chenming Hu

  10. The “fundamental” 60mV/decade Limit VG COX Ec Ev Source Channel Drain Electrons go over a potential barrier. Leakage current is determined by the Boltzmann distribution or 60 mV/decade, limiting MOSFET, bipolar, graphene MOSFET… How to overcome the limit: Let electrons go through the energy barrier, not over it  tunneling 10 6/2009 Chenming Hu

  11. Semiconductor Band-to-Band Tunneling EC EV A known mechanism of leakage current since 1985. J. Chen, P. Ko, C. Hu, IEDM 1985 Called Gate Induce Drain Leakage (GIDL) because the current depends on the gate voltage. 6/2009 Chenming Hu

  12. Basic Tunnel Transistor Structure P - N+ Source P+ Drain Some references W. Reddick, G. Amaratunga, Appl. Phys. Letters, vol. 67, 1994. W. M. Reddick, et al., Appl. Phys. Lett., vol. 67(4), pp. 494-497, 1995. C. Aydin, A. Zaslavsky, et al., Appl. Phys. Lett., vol. 84(10), pp. 1780-82, 2004. WY. Choi et al., Tech. Dig. Int. Electron Device Meet, pp. 955-958, 2005. K. K Bhuwalka, et al., Jpn. J. of Appl. Phys., vol. 45(4B), pp. 3106-3109, 2006. Th. Nirschl, et al., Electron Device Letters, vol. 28(4), p. 315, 2007. ~100X less current than MOSFET Need a more optimal tunneling transistor structure. 12 6/2009 Chenming Hu

  13. Green Transistor (gFET)--Simulation P+ Pocket P+ Pocket Gate P - N+ P+ Buried Oxide Hole flow Electron flow P+ Drain N+ Source Simulated carrier generation rates G C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008 S D Energy band diagram Large field, good capacitive coupling between gate and pocket, abrupt turn-on due to over-lap of valence/conduction bands, adjustable tun-on voltage. 13 6/2009 Chenming Hu

  14. gFET vs Basic Tunnel FET-simulation EOT= 1 nm VDD=1V Lg=40nm EOT= 4.5 nm VDD=4V gFET Drain Current, IDS (A/µm) Basic Tunnel FET * Gate Voltage, VGS (V) C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008 * K. K Bhuwalka, et al., Jpn. J. of Appl. Phys., vol. 45(4B), pp. 3106-3109, 2006 6/2009 Chenming Hu

  15. Drain Current, IDS (µA/µm) Drain-Source Voltage, VDS (V) Simulated Id-Vd of 0.5V Ge gFET EOT=0.5nm • Good output resistance and DIBL. Lg = 40nm C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008 6/2009 Chenming Hu

  16. Vdd (Power) Scaling Path: Reduce Band Gap 1E - 02 Eg=0.36eV, Vdd=0.2V, EOT=5 Å, CV/I=0.42pS 1E - 03 1E - 04 1E - 05 Eg=0.69eV, Vdd=0.5V, EOT=7 Å, CV/I=2.2pS Drain Current, IDS (µ/µm) 1E - 06 Eg=1.1eV, Vdd=1V, EOT=10 Å, CV/I=4.2pS 1E - 07 Ids (A/um) 1E - 08 Eg=0.36eV (InAs) 1E - 09 Lg=40nm Eg=0.69eV (Ge) 1E - 10 Silicon 1E - 11 0.0 0.2 0.4 0.6 0.8 1.0 Gate Voltage, VGS (V) C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008 6/2009 Chenming Hu

  17. Hetero-tunneling gFET Gate P+ Source N+ Drain A B Substrate Gate Oxide Egeff Gate B A • In lieu of low Eg semiconductor, a heterojunction can provide a very small effective tunneling band gap, Egeff. EC EV Egeff is 0.3eV for Si/Ge hetero-tunneling gFET. A. Bownder et al., 8th International workshop Junction Technology, Extended Abstracts , p.93, 2008. Also IEEE Silicon Nanoelectronics Workshop, 2008. 6/2009 Chenming Hu

  18. Compound Semiconductors Egeff • Wide choices of heterojunction materials, band engineering and strain engineering. • Example: InAs-AlGaSb provides tunable Egeff from positive to negative values. • Very low voltage gFET may be possible. 18 6/2009 Chenming Hu

  19. Ge-Source Tunnel Transistor Source Gate Drain P+ Ge N+ Si Si SiO2 Es = |VGS+Vtunnel|/(Toxege/eox) VD=0.5V LG=5mm W=0.33mm Vtunnel ~ 0.6V S [mV/dec] ID [A/mm] ID [A/mm] Experiment Model VGS [V] S. Kim et al., VLSI Tech Symp., 2009

  20. Green’s Function Based Simulation Sayeef Salahudin

  21. Summary • ICs use of world’s electricity is several % and growing fast. • A low voltage transistor can slow the growth. • Green Transistor may potentially provide orders-of-magnitude IC power reduction. 6/2009 Chenming Hu

More Related