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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Course and contest Results of Phase <1> <Ayad Mostafa, Florian Grützmacher>. Facts to present. Design and architecture: Chosen Adder: Ripple Carry Adder - works - expected speed:slow Chosen Multiplier: Booth-Wallace
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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase <1> <Ayad Mostafa, Florian Grützmacher>
Facts to present • Design and architecture: • Chosen Adder: Ripple Carry Adder • - works • - expected speed:slow • Chosen Multiplier: Booth-Wallace • - doesn’t work yet!
Facts to present • Figures to be given (with units): • Facts involve your_design.vhd with Ripple-Carry-Adder but without a multiplier
Flow for the presentation • Recommended flow for reasoning: • Observations: • A very fast adder • Discuss results • Virtex 6 FPGA have a Carry-Path • Ripple-Carry may be optimized to this path • -> very fast adder • BUT: on ST65 probably slow because of no carry-path optimization • Outlook on next steps/optimizations • Implementing another adder like CLA • Implementing a multiplier