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STR71x Training

STR71x Training. MCD Application v1.2 – March 2004. CONTENTS. Objectives STR71x Device STR71x Family Block Diagram APB Buses Memory mapping and boot modes STR71x Library Library Structure Use Example STR71x Peripherals Features Software Library Programming Example. CONTENTS.

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STR71x Training

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  1. STR71x Training MCD Applicationv1.2 – March 2004

  2. CONTENTS • Objectives • STR71x Device • STR71x Family • Block Diagram • APB Buses • Memory mapping and boot modes • STR71x Library • Library Structure • Use Example • STR71x Peripherals • Features • Software Library • Programming Example

  3. CONTENTS • Objectives • STR71x Device • STR71x Family • Block Diagram • APB Buses • Memory mapping and boot modes • STR71x Library • Library Structure • Use Example • STR71x Peripherals • Features • Software Library • Programming Example

  4. OBJECTIVES • Introduce the STR71x family • Improve your knowledge on STR71x peripherals • Introduce the STR71x Software Library • At the end of the training you will be able to : • List the main features of the STR71x peripherals and core • Configure the software library environment • Develop your applications using the STR71x Software Library

  5. CONTENTS • Objectives • STR71x Device • STR71x Family • Block Diagram • APB Buses • Memory mapping and boot modes • STR71x Library • Library Structure • Use Example • STR71x Peripherals • Features • Software Library • Programming Example

  6. 100,000 cycles endurance No wait state for embedded RAM and FLASH 3.3V application supply and I/O interface Embedded 1.8V voltage regulator for core supply STR71x Family ARM7TDMI 16/32 bit RISC CPU based host Micro • High Performance • Low Power Consumption

  7. ARM7TDMI CPU EMI PRCCU FLASH JTAG ARM7 native bus RAM APB1 APB2 I2C0 ADC I2C1 EIC BSPI0 TIM0 BSPI1 TIM1 UART0 TIM2 TIM3 UART1/SC APB bus APB bus UART2 RTC UART3 XTI USB WDG CAN GPIO0 HDLC GPIO1 GPIO2 STR71x STR71x Block Diagram • ARM7TDMI 16/32 bit RISC CPU ARM7TDMI CPU EMI PRCCU • Embedded Memory • FLASH : 256 kBytes + 16 kBytes FLASH RAM • RAM : 64 kBytes • EMI (TQFP144 only) : support of up to 4 banks of external SRAM, FLASH APB1 APB2 • Power Supply with low power modes : • 3.0V to 3.6V for I/Os • 3.0V to 3.6V for ADC • 1.8V for CPU and peripherals • 0-48 MHz frequency managed by PRCCU and PLL • 2 APB bridges : • APB1: communication peripherals • APB2: general purpose peripherals

  8. ARM7TDMI CPU EMI PRCCU FLASH JTAG ARM7 native bus RAM I2C0 APB1 APB2 I2C0 ADC12 I2C1 I2C1 EIC BSPI0 TIM0 BSPI0 TIM0 BSPI1 TIM1 BSPI1 TIM1 UART0 TIM2 UART0 TIM2 TIM3 UART1/SC TIM3 UART1/SC APB bus UART2 APB bus UART2 RTC UART3 UART3 XTI USB WDG GPIO0 CAN GPIO0 GPIO1 HDLC GPIO1 GPIO2 GPIO2 STR71x STR71x APB Buses • Connect native bus to devices • Clock Gating for peripherals • 4 kBytes for each mapped peripheral and dedicated registers APB 1 APB 2 - 2 x I²C ADC12 - 2 x BSPI EIC - 4 x UART - 1 x USB - 1 x CAN - 1 x HDLC RTC - 1 x 12-bits Analog to Digital Converter XTI -Enhanced Interrupt Controller USB WDG -4 x 16-bit Timers - Real Time Clock CAN - External Interrupts HDLC - Watchdog Timer - Up to 3 16-bit GPIOs

  9. EIC 0xFFFF FFFF EIC APB2 0xFFFF FC00 RAM FLASH EXTMEM APB2 APB1 0xE000 0000 APB1 RCCU 0xC000 0000 EXTMEM RCCU 0xA000 0000 0x6000 0000 EXTMEM FLASH 0x6000 0000 0x4000 0000 EN B1 B0 RAM FLASH 0x2000 0000 0x4000 0000 Boot MEM 0x0000 0000 RAM 1 1 1 1 1 x x 1 0 x x 0 x 0 x 0x2000 0000 0x0000 0000 0x0000 0000 0x0000 0000 Boot MEM 0x0000 0000 Reserved Memory Mapping and Boot Modes • Addressable memory space of 4 GBytes • RAM : 64 kBytes • FLASH : 256 kBytes + 16 kBytes • EXTMEM : 64 MBytes in 4 banks Boot modes A copy of RAM, EXTMEM or FLASH will be aliased at 0x0 Depending on BOOTEN, BOOT0 and BOOT1 pins: Memory remapping Memory remapping can be done by software by programming the boot bits in the BOOTCR register

  10. CONTENTS • Objectives • STR71x Device • STR71x Family • Block Diagram • APB Buses • Memory mapping and boot modes • STR71x Library • Library Structure • Use Example • STR71x Peripherals • Features • Software Library • Programming Example

  11. Application Layer User Application Interface Software Layer Function 1 Function 2 … Function m Function 1 Function 2 … Function k Driver 1 Driver n Hardware Layer Peripheral 1 Peripheral i Peripheral n Library Structure (1) • Standard C language (only system parts are written in assembly) • Easy tool to access the peripheral functions • For each peripheral, a set of functions is defined to cover its features • Consistency in naming convention to make the code maintenance easier • Reduce the development time of new applications

  12. Application Layer application.c 71x_conf.h 71x_it.c 71x_lib.h 71x_map.h Software Layer 71x_type.h gpio.h 71x_lib.c 71x_it.h Hardware Layer gpioX Library Structure (2) • Global headers (includes all) • 71x_init.s: initializes modes and branches to main() • 71x_vect.s: exception vectors • retarget.c: retarget layer • scat.scf: specifies the memory mapping of the image to the linker • Peripheral driver source code • Interrupt functions’ headers • Peripheral functions’ headers • Interrupt functions source code • Peripheral registers’ addresses • Common types and constants • Configuration file • Peripherals pointers initialization • User application source code gpio.c

  13. Interrupt Handling Example 71x_vect.s 71x_it.c 0x18 Branch to IRQHandler subroutine IRQHandler “IRQ mode” User program “SYS mode” Instruction Subtract 4 from lr_irq TIMIRQHandler IRQ request Instruction Save r[0:12], spsr_irq and lr_irq Switch to SYS mode to allow other IRQ interrupts Execute the instruction located in IVR Instruction Branch with link to TIM_IRQHandler TIMI_RQHandler Clear the pending bit TIM IRQ Handler C code Switch to IRQ mode restore r[0:12], spsr_irq and lr_irq pc  lr_irq cpsr  spsr_irq

  14. Library Use Example (1) • Common files must be copied to the working directory • To use the peripheral PPPx • Copy ppp.c and ppp.h files to the working directory • Edit the 71x_conf.h file and uncomment the following lines : • #define _PPP (mandatory) • #define _PPPx (optional, depending on the peripheral) • If you want to debug your application, you have to define the label DEBUG in the 71x_conf.h file : • #define DEBUG • Include this line in your application source code : • #include <71x_lib.h>

  15. 71x_conf.h #define DEBUG #define _GPIO /* include gpio.h file */ #define _GPIO0 /* use GPIO0 peripheral */ 71x_map.h typedef volatile struct { u16 PC0; u16 EMPTY1; u16 PC1; u16 EMPTY2; u16 PC2; u16 EMPTY3; u16 PD;} GPIO_TypeDef; #define GPIO0_BASE (APB2_BASE + 0x3000) #ifdef DEBUG #ifdef _GPIO0 EXT GPIO_TypeDef *GPIO0; #endif /* _GPIO0 */ #else /* NON DEBUG */ #define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE) #endif /* DEBUG */ Library Use Example (2) • 71x_lib.h #include "71x_type.h" #include "71x_conf.h" #include "71x_map.h" #ifdef _GPIO #include "gpio.h" #endif To be modified by user Do not modify this file Define _GPIO in 71x_conf.h to include gpio.h in your project Do not modify this file • main.c #include "71x_lib.h" int main { #ifdef DEBUG debug(); #endif // main program } User file Include 71x_lib.h only Pointers to peripherals structures are used in DEBUG mode Initialize peripheral pointers when in DEBUG mode Constants are used in NON DEBUG mode

  16. Library Programming Warnings ! • Due to the ARM reduced instruction set, a read-modify-write access to memory locations or I/Os is interruptible (split into two basic instructions), so the user may have to put within critical sections the portions of code where a risk of data corruption exists : • Disable the interrupts that could occur • Start of the critical section • Do the access • End of the critical section • Re-enable the interrupts

  17. CONTENTS • Objectives • STR71x Device • STR71x Family • Block Diagram • APB Buses • Memory mapping and boot modes • STR71x Library • Library Structure • Use Example • STR71x Peripherals • Features • Software Library • Programming Example

  18. STR71x Peripherals Power, Reset and Clock Control Unit (PRCCU)

  19. ARM7TDMI CPU EMI PRCCU FLASH JTAG ARM7 native bus RAM APB1 APB2 I2C0 ADC12 I2C1 EIC BSPI0 TIM0 BSPI1 TIM1 UART0 TIM2 TIM3 UART1/SC APB bus APB bus UART2 RTC UART3 XTI USB WDG CAN GPIO0 HDLC GPIO1 GPIO2 STR71x Power, Reset and Clock Control Unit (PRCCU) PRCCU

  20. Power, Reset and Clock Control Unit • Separate Power Block with enhanced power saving features • Reset Management block with Hardware and software reset sources • Clock Control Unit with a wide range of clock frequency and sources

  21. Reset Unit • Hardware and Software Reset • Reset pad (Input only) with an analog filter to improve EMC susceptibility • Internal Watchdog Reset • Low Voltage Detector Reset

  22. OSC 32kHz RTC RTCXI PRCCU RTCXO CK_AF MCLK MCLK DIV2/4/8 to Core and Memories 1/16 RCLK PCLK1 DIV2/4/8 to Fast Peripherals on APB1 CLK3 CLK2 PCLK2 1/2 CK DIV2/4/8 to Slow Peripherals on APB2 PLL1 PLL1 CKOUT HDLC PLL2 PLL2 HCLK 48MHz USB USBCLK Clock Control Unit • Two separate PLLs : • PLL Multiplier of 12,16, 20 and 28 • PLL Divider from 1 to 7 • 4 clock sources • Main clock system up to 48 MHz • Separate clock activation for each peripheral

  23. Control Unit Frequency Limits

  24. 3.3V IO RING Main Regulator Low Power Regulator Main Regulator Low Power Regulator Core 1.8V 1.8V 1.8V Backup IO RTC Low Power Logic Power Block • Single External 3.3 V power supply and I/O capability • 4 Power Saving Modes : • Slow • Wait For Interrupt • Stop • Standby • 2 Embedded regulators with external 1.8V capacitors • Main Voltage Regulator • Low Power Voltage Regulatior 3.3V 1.8V Backup IO RTC Low Power Logic

  25. Low Power Modes (1/3) RUN Full power mode WFI Mode You reduce power consumption by stopping the core. Peripherals are kept running and the register contents are preserved Slow Mode You reduce power consumption by slowing down the main clock Stop Mode You stop all clocks without resetting the device, hence preserving the MCU status. The internal power is maintained Standby Mode In Standby mode, the main Voltage Regulator is switched off internally, and the kernel of the device is powered off. Exit with RTC, WAKEUP IT, Reset

  26. Low Power Modes (1/3) • Wait For Interrupt Mode (WFI) • CPU forced to the wait mode • Software configurable Internal slow clock or external RTC clock • Automatic context saving • Resume events : External Wake-up pin, RTC alarm • Software configurable Low Power Mode activation • SLOW Mode • Software configurable slow clock selection • 3 different slow clock sources : CLK2, CLK2/16, CK_AF • Low Power WFI Mode • Combination of WFI and SLOW Modes

  27. Low Power Modes (3/3) • STOP Mode • All system clocks are stopped • Power supply is maintained for the whole chip • Automatic context saving • Resume events : external Wake-up pin, RTC alarm • Configurable Exit STOP mode interrupt • STAND BY Mode • All system clocks are stopped • All I/O pads forced to High impedance • V18 Power supply is switched off • Separate Power supply for backup block • System status monitored by the nSTDBY pad

  28. Low Power Modes Summary

  29. PRCCU Programming Example This example configures the Clock Control Unit to generate 40 MHz for the main system clock and 20 MHz for APB1 and APB2 peripherals with CK = 16 MHz. Configuration Steps Programming Steps { • Select the Clock2 as active clock RCCU_RCLKSourceConfig(RCCU_CLOCK2); • Configure the PLL1 parameters RCCU_PLL1Config(RCCU_Mul_20, RCCU_Div_4); • Select the PLL1 output clock as active clock RCCU_RCLKSourceConfig(RCCU_PLL1_Output); • Main system Clock is equal to PLL1 output clock RCCU_MCLKConfig(RCCU_DEFAULT); • APB2 Clock is equal to PLL1 output clock divided by 2 RCCU_PCLKConfig(RCCU_RCLK_2); RCCU_FCLKConfig(RCCU_RCLK_2); } • APB1 Clock is equal to PLL1 output clock divided by 2

  30. STR71x PeripheralsExternal Memory Interface(EMI)

  31. ARM7TDMI CPU EMI PRCCU FLASH JTAG ARM7 native bus RAM APB1 APB2 I2C0 ADC12 I2C1 EIC BSPI0 TIM0 BSPI1 TIM1 UART0 TIM2 TIM3 UART1/SC APB bus APB bus UART2 RTC UART3 XTI USB WDG CAN GPIO0 HDLC GPIO1 GPIO2 STR71x External Memory Interface (EMI) EMI

  32. EMI Features • 4 external regions/chip select (memory banks) • Each bank is fully configurable : • Can address up to 16 MBytes external memory space • Up to 15 wait states in read/write cycles • Programmable data bus size (16 or 8 bits) • Independent enabling/disabling

  33. MCLK C_Length[3:0] 0x3 B_Size[1:0] 0x1 RDn Access Length (3 wait states) CSn2 WEn0 WaitCycle WaitCycle WaitCycle WEn1 A[1:0] 0x0 A[23:2] Address[23:2] D[15:0](output) Data[15:0] EMI Access Cycles Timing diagram of a 16-bit write cycle on a 16-bit external memory, with 3 wait states.

  34. BCR0 BCR1 BCR1 BCR0 15 15 15 15 14 14 14 14 13 13 13 13 12 12 12 12 11 11 11 11 10 10 10 10 9 9 9 9 8 8 8 8 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 0 BE BE 1 - - - - C_LENGTH x C_LENGTH 5 0 x B_SIZE B_SIZE EMI Programming Example This example shows how to access the EMI. Configuration Steps Programming Steps { GPIO_Config(GPIO2, 0x000F, GPIO_AF_PP); • Configure the I/Os as Alternate Function • Disable Bank 0 EMI_Config(0, EMI_DISABLE); • Enable Bank 1 with 5 wait state and 8-bit data bus EMI_Config(1, EMI_ENABLE | EMI_WAITSTATE(5) | EMI_SIZE_8); • Write 0x12345678 data to Bank 1 *(u32*)(0x62000000) = 0x12345678; data = *(u32*)(0x62000000); } • Read data from Bank 1 ! Don’t forget to configure the GPIO2 port pins as Alternate Function Push-Pull

  35. STR71x PeripheralsOn-chip Flash Memory

  36. ARM7TDMI CPU EMI PRCCU FLASH JTAG ARM7 native bus RAM APB1 APB2 I2C0 ADC12 I2C1 EIC BSPI0 TIM0 BSPI1 TIM1 UART0 TIM2 TIM3 UART1/SC APB bus APB bus UART2 RTC UART3 XTI USB WDG CAN GPIO0 HDLC GPIO1 GPIO2 STR71x On-chip Flash Memory FLASH

  37. Flash Features • 2 separate banks : • Bank 0 : containing 256 kBytes of memory divided in 8 sectors • Bank 1 : containing 16 kBytes of memory divided in 2 sectors • Internal management of write (program or erase) sequence. • Erase operation on sectors (each sector can be erased independently). • Program operation on single word (32-bits) or double word (64-bits). • Suspend of on-going write operation • You can read from one bank while writing to the other. • 2 operating modes : • Random: read operation are performed with zero wait states up to 33 MHz • Burst: sequential accesses are performed with zero wait states up to 48 MHz • 2 protection strategies : • Write protection: A sector can be write Protected • Debug protection: debug features and JTAG pins are disabled

  38. Flash Programming Example The following example writes data to the sector 0 and 1 then erases all the flash module. Configuration Steps Programming Steps { FLASH_Init(); • Initialize the Flash registers • Write 0x12345678 data to the sector 0, bank 0 of the Flash module FLASH_WordWrite(0x00000000, 0x12345678); • Write 0x87654321 data to the sector 0, bank 1 of the Flash module FLASH_WordWrite(0x000C0000, 0x87654321); • Erase all the Flash Module FLASH_ModuleErase(); }

  39. STR71x PeripheralsAdvanced Peripheral Bus(APB)

  40. ARM7TDMI CPU EMI PRCCU FLASH JTAG ARM7 native bus RAM APB1 APB2 APB1 APB2 I2C0 ADC12 I2C1 EIC BSPI0 TIM0 BSPI1 TIM1 UART0 TIM2 TIM3 UART1/SC APB bus APB bus APB bus APB bus UART2 RTC UART3 XTI USB WDG CAN GPIO0 HDLC GPIO1 GPIO2 STR71x APB Overview • The APB bridges allows the connection between the ARM7 native bus and peripherals mapped on the APB buses. • 2 separate bridges : • APB1 : For fast peripherals such as I²C, UART, USB, CAN, SPI, HDLC. • APB2 : For slow peripherals such as EIC, XTI, GPIOs, ADC12, Timer, RTC, Watchdog.

  41. APB Bridges Features • Peripheral Clock: The APB bridges controls the clock gating for all the peripherals. Each peripheral’s clock signal can be activated or disabled through the CKDIS register. • Peripheral Reset: The APB bridges control the Reset for all the peripherals. Each peripheral can be configured through the SWRES register to be reset or not.

  42. 1 1 1 1 0 APB Programming Example The following example configures the clock and reset for the UART0 and UART1 peripherals (on APB1). Configuration Steps Programming Steps { APB_ClockConfig(APB1, UART0_Periph | UART1_Periph, DISABLE); • Disable the Clock of the UART0 and UART1 peripherals APB_ClockConfig(APB1, UART2_Periph, ENABLE); • Enable the Clock for the UART2 APB_SwResetConfig(APB1, UART0_Periph | UART1_Periph, ENABLE); • The UART0 and UART1 are kept under Reset APB_SwResetConfig(APB1, UART2_Periph, DISABLE); } • Disable reset status for the UART2 CKDIS CKDIS SWRES X X

  43. STR71x Peripherals12-bit Analog-to-Digital Converter(ADC12)

  44. ARM7TDMI CPU EMI PRCCU FLASH JTAG ARM7 native bus RAM APB1 APB2 I2C0 ADC12 I2C1 EIC BSPI0 TIM0 BSPI1 TIM1 UART0 TIM2 TIM3 UART1/SC APB bus APB bus UART2 RTC UART3 XTI USB WDG CAN GPIO0 HDLC GPIO1 GPIO2 STR71x Analog-to-Digital Converter (ADC) ADC12

  45. Sleep_mod VCM Vref Data Register 0 Data Register 0 P0.0 P0.0 ∑ - ∆ Modulator ∑ - ∆ Modulator Data Register 1 Data Register 1 Sinc3 Filter Sinc3 Filter P0.1 P0.1 Mux Output Data Register 2 Data Register 2 P0.2 P0.2 P0.3 P0.3 Data Register 3 Data Register 3 Clock Prescaler Register Control/Status Register IRQ IRQ ADC12 Features • 4 Data registers to store conversion result for each channel • 12-bit resolution • Input voltage range : 0 - 2.5V • 4 Flags showing the availability of conversion result • Sigma-Delta Architecture • 4 Analog input channels • Clock configuration: PRESCALER = APB2_FREQ / (SAMPLE_FREQ * 512 * 4) • 2 Conversion modes : • Round-robin (up to 500 Hz / 2 ms) • End of conversion interrupt • Single channel (up to 2 kHz / 500 µs) Clock Prescaler Register Control/Status Register

  46. Select Input Channel Select Input Channel Reset Modulator Reset Modulator Clear Digital Filter Clear Digital Filter Acquire Analog Data Acquire Analog Data Sinc3 Filter Sinc3 Filter Output 16-bit Sample Output 16-bit Sample Reset Converter Shift Input Channel ADC12 Operation Modes • Single Channel Operation • Normal Operation (Round Robin) 512 oversampling clock cycles Taken out every2048 clock cycles

  47. CSR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BOOTCR x x x x x x 1 x x x x x 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x 0 x x x x BOOTCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CPRR - PKG64 X HDLC CAN ADCEN LPOW USB SPI0 BOOT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x PRESC[6:0] BOOTCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x 1 x x x x CSR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - OR - IE[3:0] - AXT A[1:0] DA3 DA2 DA1 DA0 CPRR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x 0 0 1 0 0 0 0 CSR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x 1 x x x DATA3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA[11:0] - CSR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X x x x x x x 1 1 x x x x ADC12 Programming Example This example shows how to use the analog-to-digital converter in the single channel mode. Configuration Steps Programming Steps { ADC12_Init(); • Initialize the converter • Configure the I/O port to analog input GPIO_Config(GPIO1, 0x0001, GPIO_HI_AIN_TRI); • Enable the converter ADC12_ConversionStart(); • Configure the prescaler ADC12_PrescalerConfig(500); • Configure mode of conversion ADC12_ModeConfig(ADC12_SINGLE); • Select channel to be converted ADC12_ChannelSelect(ADC12_CHANNEL0): while (!ADC12_FlagStatus(ADC12_DA0)); • Wait until the Data Available flag is set ADC12_ConversionValue(ADC12_CHANNEL0); • Get the conversion result ADC12_ConversionStop(); } • Disable the converter ! Don’t forget to configure the GPIO1 port pins as High Impedance Analog Input

  48. STR71x PeripheralsEnhanced Interrupt Controller(EIC)

  49. ARM7TDMI CPU EMI PRCCU FLASH JTAG ARM7 native bus RAM APB1 APB2 I2C0 ADC12 I2C1 EIC BSPI0 TIM0 BSPI1 TIM1 UART0 TIM2 TIM3 UART1/SC APB bus APB bus UART2 RTC UART3 XTI USB WDG CAN GPIO0 HDLC GPIO1 GPIO2 STR71x Enhanced Interrupt Controller(EIC) EIC

  50. SIR Interrupt Vector Table (32 entry) Interrupt Vector Table (32 entry) Interrupt from line IRQn IRQn vector … IVR IVR[31:16] IVR[31:16] SIR[31:16] SIR[31:16] Highest priority interrupt IER IPR CIPR IRQ0 IE0 IE0 IP0 IP0 Current Interrupt Priority Current Interrupt Priority Priority Stack (16 entry) Priority Stack (16 entry) Stack Control (PUSH/POP) IRQ1 IE1 IE1 IP1 IP1 IRQ Control logic IRQ Control logic … … … … … … IRQ Request IRQ to ARM core IRQ31 IE31 IE31 IP31 IP31 ICR FIQ_EN FIQ_EN IRQ_EN IRQ_EN FIR FIP FIQ to ARM core FIQ Request FIQ Control logic FIQ Control logic FIQ0 FIE0 FIE0 FIP0 FIP0 FIQ1 FIE1 FIE1 FIP1 FIP1 EIC Features • Hardware handling of multiple interrupt channels, interrupt priority and automatic vectorization. • 32 maskable interrupt channels, mapped on ARM’s interrupt request pin IRQ. • 16 programmable priority levels for each interrupt channels mapped on IRQ. • Hardware support for interrupt nesting (15 levels). • 2 maskable interrupt channels, mapped on ARM’s fast interrupt request pin FIQ, with neither priority nor vectorization.

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