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ECE734 Course Project: A Survey on Retiming — Algorithm and Applications. James D. Z. Ma Department of Electrical and Computer Engineering University of Wisconsin — Madison. Outline. Introduction to retiming Fundamental algorithms of retiming
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ECE734 Course Project: A Survey on Retiming — Algorithm and Applications James D. Z. Ma Department of Electrical and Computer Engineering University of Wisconsin — Madison
Outline • Introduction to retiming • Fundamental algorithms of retiming • Non-trivial extensions of retiming algorithms • Application of retiming techniques to VLSI/DSP • Project progress
Definitions and Applications • Retiming • Change locations of delay elements in a circuit without affecting the functionality of the circuit • Clock period minimization • Register count minimization • Switching activity and power reduction • Logic synthesis
First Retiming Algorithm • For clock period and register count minimization • Charles E. Leiserson and James B. Saxe, “Optimizing synchronous circuitry by retiming”, in The Third Caltech Conference on VLSI, pp. 87-116, 1983 • Two quantities • W(u,v): minimum number of registers on any path from node u to node v • D(u,v): maximum computation time among all paths from node u to node v with weight W(u,v)
Algorithm Outline • Compute W and D based on all-pair-shortest-path algorithm • Sort the values of D(u,v) • Binary search these values to find a retiming solution with the minimum clock period by solving a system of inequalities, based on linear programming framework More efficient algorithm to be presented in the report
Non-Trivial Extensions of the Fundamental Retiming Algorithm • Consider different constraints on delay elements, initial states, setup and hold • Consider manufacturing effect — probabilistic retiming • Incorporate interconnect delay and clock skew into retiming • Multi-dimensional retiming • Scheduling, (un)folding, and retiming
Applications of Retiming • Resynthesis for sequential network optimization using combinational techniques • Retiming for power and switching activity reduction • Scheduling, (un)folding, and parallelism • Embedded system and communications • Software pipelining, partial scan, TPG, BIST, equivalence checking, FPGA technology mapping, physical design automation
Project progress • Literature search — done • Fundamental algorithms and non-trivial extensions — done • Applications — in progress Thank you!
