Modern Physical Design: Algorithm Technology Methodology (Part II)

1. Modern Physical Design: AlgorithmTechnologyMethodology(Part II) Stan Chow Ammocore Andrew B. Kahng UCSD Majid Sarrafzadeh UCLA

2. PART II: Fundamental Physical Design Formulation and Algorithms Placement • Motivation • Formulation • Algorithms • Complexity management • Challenges • Routing • Motivation • Formulation • Algorithms • Complexity management • Challenges

3. Front End Flow Back End Flow Behavioral Level Design IO Pad Placement Logic Design and Simulation Power/Ground Stripes, Rings Routing Logic Synthesis Logic Partitioning Die Planning Global Placement Detail Placement Simulation Floorplanning Clock Tree Synthesis and Routing Design Verification Timing Verification Extraction and Delay Calc. Timing Verification Global Routing Test Generation LVS DRC ERC Detail Routing Front End Back End

4. Prediction and Cost Functions

5. Prediction • What is prediction ? • every system has some critical cost functions: Area, wirelength, congestion, timing etc. • Prediction aims at estimating values of these cost functions without having to go through the time-consuming process of full construction. • Allows quick space exploration, localizes the search • For example: • statistical wire-load models • Wirelength in placement

6. Paradigms of Prediction • Two fundamental paradigms • statistical prediction • #of two-terminal nets in all designs • #of two-terminal nets with length greater than 10 in all designs • constructive prediction • #of two-terminal nets with length greater than 10 in this design • … and everything in between, e.g., • #of critical two-terminal nets in a design based on statistical data and a quick inspection of the design in hand. • “Absolute truth” or “I need it to make progress” • SLIP (System Level Interconnect Prediction) community.

7. Statistical Prediction • W. E. Donath , A. B. Kahng, J. Mehndl , et al. • Developing theoretical/statistical/observational models for interconnect estimation. • Basic types • Estimation of Global Parameters. Assumes homogenous designs. • Rent’s rule • Average multiplicity of a netlist is 2.2 - 2.6 • Design Specific. Assumes localized homogeneity • localized Rent’s rule • A specific Verilog block has average multiplicity 3.2

8. Statistical Prediction (cont) • Shortcomings • circuits are not homogeneous. • they have been designed/defined hierarchically. • higher connectivity at lower levels. • these features are difficult to model statistically across designs and too expensive to predict for one design. • Positive Aspects • very fast • reasonable approximation

9. Constructive Prediction • Generally: the concept of fast algorithms • a quick/low-temperature annealing. • Final routabililty is correlated with first-level mincut? • SLIP position statement and some recent results (a few ideas will be discussed). • E.g., Floorplan based on a given verilog hierarchy • E.g., Construct fast layouts to predict final timing violations, routability information, etc.

10. Constructive Prediction (cont) • Usefulness • xKy (K means knowledgeable) type of applications which may require some critical parameters from x to be fed back to y engine. • Allows quick exploration. • The predictor itself can act as the front-end for final Construction (time spent is not really wasted). • Shortcomings • Slow • Can we trust it? (low-temperature annealing) • Would it localize the search too much?

11. Placement Paradigms

12. VLSI Design Flow and Physical Design Stage • Definitions: • Cell: a circuit component to be placed on the chip area. In placement, the functionality of the component is ignored. • Net: specifying a subset of terminals, to connect several cells. • Netlist: a set of nets which contains the connectivity information of the circuit. IO Pad Placement Power/Ground Stripes, Rings Routing Global Placement Detail Placement Clock Tree Synthesis and Routing Extraction and Delay Calc. Timing Verification Global Routing Detail Routing

13. Placement Problem • Input: • A set of cells and their complete information (a cell library). • Connectivity information between cells (netlist information). • Output: • A set of locations on the chip: one location for each cell. • Goal: • The cells are placed to produce a routable chip that meets timing (low-power, …) • Challenge: • The number of cells in a design is very large (> 1 million). • The timing constraints are very tight.

14. Placement Problem A good placement A bad placement

15. Global and Detailed Placement Global Placement Detailed Placement In global placement, we decide the approximate locations for cells by placing cells in global bins. In detailed placement, we make some local adjustment to get the final non-overlapping placement.

16. Placement Cube (4d) Layout Coarseness Netlist Granularity Cost Function Algorithm • Cost Function(s) to be used • Cut, wirelength, congestion, crossing, ... • Algorithm(s) to be used • FM, Quadratic, annealing, …. • Granularity of the netlist • Coarseness of the layout domain • 2x2, 4x4, …. • An effective methodology picks the right mix from the above and knows when to switch from one to next. • Today: Ad-hoc

17. What does the cube represent? Layout Coarseness Netlist Granularity Cost Function Algorithm

18. Twolf Global Placement Layout Coarseness Netlist Granularity Cost Function Algorithm • Two points in the entire cube • Annealing, WL, mxm, clusters • Annealing, WL, mxm, cells

19. Traditional Algorithms Layout Coarseness Netlist Granularity Cost Function Algorithm • Quadratic Placement • Simulated Annealing • Bi-Partitioning / Quadrisection • Force Directed Placement • Hybrid

20. Quadratic Placement B = x = Min [(x1-x3)2 + (x1-x2)2 + (x2-x4)2] : F • Analytical Technique x3 x1 dF/dx1 = 0; dF/dx2 = 0; Ax = B x2 x4 2 -1 -1 2 A = x3 x4 x1 x2

21. Analytical Placement • Get a solution with lots of overlap • What do we do with the overlap?

22. Pros and Cons of QP • Pros: • Very Fast Analytical Solution • Can Handle Large Design Sizes • Can be Used as an Initial Seed Placement Engine • Cons: • Not Suitable for Timing Driven Placement • Not Suitable for Simultaneous Optimization of Other Aspects of Physical Design (clocks, crosstalk…) • Gives Trivial Solutions without Pads (and close to trivial with pads)

23. Initial Placement Improved through • Swaps and Moves • Accept a Swap/Move if it improves cost • Accept a Swap/Move that degrades cost under some probability conditions Simulated Annealing Placement Cost Time

24. Pros and Cons of SA • Pros: • Can Reach Globally Optimal Solution (given “enough” time) • Open Cost Function. • Can Optimize Simultaneously all Aspects of Physical Design • Can be Used for End Case Placement • Cons: • Extremely Slow Process of Reaching a Good Solution

25. Bi-Partitioning/Quadrisection

26. Pros and Cons of Partitioning Based Placement • Pros: • More Suitable to Timing Driven Placement since it is Move Based • New Innovation (hMetis) in Partitioning Algorithms have made this Extremely Fast • Open Cost Function • Move Based means Simultaneous Optimization of all Design Aspects Possible • Cons: • Not Well Understood • Lots of “indifferent” moves • May not work well with some cost functions.

27. Cells are dragged by forces. • Forces are generated by nets connecting cells. Longer nets generate bigger forces. • Placement is obtained by either a constructive or an iterative method. Force Directed Placement Fij i i j

28. Pros and Cons of Force Directed Placement • Pros: • Very Fast Analytical Solution • Can Handle Large Design Sizes • Can be Used as an Initial Seed Placement Engine • The force • Cons: • Not sensitive to the non-overlapping constraint • Gives Trivial Solutions without Pads • Not Suitable for Timing Driven Placement

29. Hybrid Placement • Mix-matching different placement algorithms • Effective algorithms are always hybrid

30. GORDIAN (quadratic + partitioning) InitialPlacement Partitionand Replace

31. Details of a Complete Placement Tool

32. Set level h = 1 Top-down Hierarchical Placement Approach Solve the hierarchical placement problem at level h number cells in each global bin < stopping threshold N END Y Split each global bin at level h into g smaller bins. Set level h = h+1

33. Set level h = 1 Top-down Hierarchical Placement Approach Solve the hierarchical placement problem at level h number cells in each global bin < stopping threshold N END Y Split each global bin at level h into g smaller bins. Set level h = h+1

34. Set level h = 1 Top-down Hierarchical Placement Approach Solve the hierarchical placement problem at level h number cells in each global bin < stopping threshold N END Y Split each global bin at level h into g smaller bins. Set level h = h+1

35. Original Subcircuit at B0

36. Original Subcircuit at B0 1 unit 1 unit Total Wirelength = 24 unit

37. Original Subcircuit at B0 1 unit 1 unit Total Wirelength = 21 unit

38. Length of a Level h Net 2(H-h+1) The length unit is the width/height of a global bin in the final hierarchical level (assume total number of hierarchical levels is H). 2(H-h+1) A global bin at level (h-1)

39. Length of a Level h Net 2(H-h+1) The length unit is the width/height of a global bin in the final hierarchical level (assume total number of hierarchical levels is H). 2(H-h+1) A global bin at level h

40. Length of a Level h Net (Worst Case) 2(H-h+1) Worst Case: Netlength = 2(H-h+1) A global bin at level h

41. Length of a Level h Net (Worst Case) 2(H-h+1) Statistical Average Case: Netlength = 2(H-h+1) A global bin at level h

42. Wirelength Bound in a Top-Down Approach • More nets are cut in finer levels: the number of cut nets at each level is increase by approximately 41-r, where r is the Rent’s parameter of the circuit (0.3~0.8). • The total wirelength obtained by a top-down approach is between Cut and 2H·Cut

43. Dragon2000 Set level h = 1 GP Solve the hierarchical placement problem at level h Split each global bin at level h into g smaller bins. Set level h = h+1 number cells in each global bin < stopping threshold N END Y START Global Placement (GP) Top-down hierarchical approach Detailed Placement (DP) Greedy heuristic END

44. GP Phase (Start)

45. GP Phase

46. GP Phase

47. Global Placement Phase • Start of GP: We start GP phase with four global bins (22 grid) • End of GP: We stop GP when there is less than 7 cells in each global bin • Interaction between net-cut and wirelength in GP • Final Stage

48. Original Subcircuit at B0 B1 B0 B3 B2

49. Original Subcircuit at B0 B0 B1 B3 B2

50. Approach A: Remove External Nets B0 B1 B3 B2