Digital Design Obsolescence

1. Digital Design Obsolescence John O’BoyleFor MAPLD September 2005 Military, Aerospace, and High Reliability IC Manufacturer MAPLD 2005/P1023

2. Defense Programs Still Need OLD ICs • 30 Year Old ICs Are Still in Use in many modern High Reliability, Military, and Aerospace applications. • Combining New Technologies and older devices leave Mil/Aero OEMs challenged with IC sourcing due to obsolescence. • The Fabrication of Obsolete ICs Is Not Attractive due to low returns and matching original designs. MAPLD 2005/P1023

3. Issue : Diminishing Supply • In Some Cases the Parts Just Vanish: • Take, for example, the Dual RS-422 Line Drivers to the right • National Semi unilaterally discontinued the supply of these devices on April 21, 2005. • Why? Because they simply ran out, no close monitoring of the supply • This means even the best managed programs may be vulnerable. MAPLD 2005/P1023

4. TODAY’s Key Challenge How Does a Mil/Aero OEM Obtain Reliable, Accurate Reproduction of Older Parts? or How Do They Entice the IC Foundry to Build Such Replacement Parts? MAPLD 2005/P1023

5. Factors for Consideration • Buy Entire Remaining Inventory; But that’s very expensive and many various Gov’t regs limit requisition quantities. • And, as a corollary to the RS-422 example, that is still no guarantee; demand can outstrip supply. • Use Commercial Parts From the Beginning; But they, too, are diminishing and are not suitable in all applications. • So, do we look to the foundry for a solution? • Let’s See … MAPLD 2005/P1023

6. 1. Foundry : Low VolumesA Fundamental Disconnect • An Illustration – Teledesic (the early days) • Almost 1000 satellites (Close enough for this illustration) • Assume 100 “Identical” parts per satellite, balance are other hi-rel. • Build them all in one year (Not realistic, but suitable for this example). • Spares at 100% of original build. • Complex die, Estimate die size 5 by 6 mm. • Technology: 0.25 Micron on 8-inch wafers. • Total fab, assembly, test yield = 85%. MAPLD 2005/P1023

7. Low Volumes = Low Profitabilityfor IC Mfg  This is Reality • 1000 x 100 = 100k devices • Plus 100% spares = 200k • Total die needed: 200k/85% = 236k round to 250k die • Gross die per wafer  1000 • Total 250k/1000 = 250 wafers • In 1996 top 10 IDMs (Integrated Device Mfr.) were 20 million wafers per year • 250/20 million = 0.00125% • Bottom line: Volume is insignificant for the foundries MAPLD 2005/P1023

8. 2. Lack of Process Knowledge • Modern designers use tools with IP embedded – they place blocks with 100s of transistors, or more. • Plus, design rules prohibit changes. • Important when designing a complex digital device or the time to complete would be prohibitive doing “Stick” designs. • Designers today enjoy no real process knowledge • No understanding of the nuances of the process used to make their design at the foundry. MAPLD 2005/P1023

9. “Lack” – is a Real GapAn Example: • Temp compensated bias driver – As temp changed, reference voltages A, B, and C remain unchanged. • Why? – The process had very linear negative TC for VBE which was used in a ratio between D3 and Q6 to afford ideal positive compensation. • A new designer tried to “Copy” the part but did not understand the process so the part failed to work. MAPLD 2005/P1023

10. 3. Foundry : Economic Imperatives • Wafer Throughput and Yield • Large scale manufacturing economics drive the foundries and fabs. • The fixed costs are very high and short term variable costs are significant, too. • The factories must produce many wafers just to reach breakeven. • Cardinal Rules: • “Fill the Fab” • Minimize process variations: wafers out/wafers started  100% (or As Close As Possible  “Cut the Scrap”) MAPLD 2005/P1023

11. Incredibly High Investments • Over 68 foundries listed by FSA (Fabless Semiconductor Association) today, not counting firms like Toshiba (not listed). • Today a 130/90 nm Fab Costs $3 to $4 Billion. Plus expendables. • Opportunity cost related to stopping a running fab to insert 250 wafers for an annual buy is expensive. • This is applies to most fabs, 12-inch, 8-inch and even 6-inch. MAPLD 2005/P1023

12. Breakeven Is High • Figure 1 (8 inch 0.18 micron fab): • At different wafer prices the monthly breakeven moves from $15 Million and 15k wafers for $1k Per wafer to $16 Million for 20k wafers at $800 each. MAPLD 2005/P1023

13. Breakeven is Very High • Figure 2 (12 inch 90 nm fab): • At $2500 per wafer the monthly breakeven Is $40 Million for 17k wafers and at $1500 breakeven will not be achieved until the variable costs come down. Yikes! MAPLD 2005/P1023

14. 4. Foundry : Scarce Expertise • Today’s Obsolete Device Designer relies on modern tools and experience and knowledge about process – a True Artisan. • Gone Are the Days of  Pencil & paper and Karnaugh maps (Min-sums); Mylar Grids with Mylar transistors and hand-drawn resistors; “Digitizers” and Rubyliths; 500x cameras that floated on Hg; chrome masters and glass plate masks. MAPLD 2005/P1023

15. Tackling Obsolescence Today– A Few Solutions • Size Does Matter – Hi-Rel volumes too small to be attractive. So think SMALL • Emulate – Works when no other solutions are available. • Create – NEW APPROACH; Much closer to original and more reasonable in investment. MAPLD 2005/P1023

16. 1. Solution – Size Does Matter • The Large Foundries (TSMC, UMC, SMIC, etc.) are out of reach to small Hi-Rel OEMs. • Small “Research Oriented” Foundries (Typically under 10,000 wafers a year, sometimes much lower) will still run special lots. • Caution: Their processes are not as well controlled as modern flows, but they are better than anything else available. MAPLD 2005/P1023

17. 2. Solution – Emulate … • There are a couple of approaches available which allow a design team to emulate an obsolete part, right down to the timing delays. • Works well for logic, the analog function is still in question, but they’re working on that too. • There are availableprogrammable approaches. • May be a possible low volume obsolete parts replacement. MAPLD 2005/P1023

18. 3. NEW APPROACH: The Multi-Project Die (“MPD”) • Amortize Mask Tool Costs Across Several Parts • Derive several different options from “MPW” Die • Metal mask programmable – Allows wafer hold at metal and patterning to meet orders – Quick Turns • Higher WSM (Wafer Starts per Month) figures to foundry partner • Not constrained by Max GDPW (Gross Die Per Wafer) • Flexible Family Sets; Memories, sequential and combinatorial logic – 34 different parts on first MPD. MAPLD 2005/P1023

19. Options for MPD • I/Os: • TTL Totem Pole • DTL • Multiple I/Os • PROM – Metal Mask • Core covers major and Minor densities in range (S, M, L) • Fusible links next • Foundry holds average of 24 wafers at metal. When down to 12, they start another 24. Four Peripheral Drivers, One Wafer: QP1631, QP1632, QP1633 and QP1634 MAPLD 2005/P1023

20. Metal Options (OP 1) Note, One Connection Scheme in OP 1 MAPLD 2005/P1023

21. Metal Options (OP 2) And Another Scheme in OP 2 MAPLD 2005/P1023

22. Summary • Economies of scale are opposite between a foundry and an obsolete device maker. • Partnering with the right manufacturing partner is key • An obsolete device designer needs process knowledge to tailor the design to take advantage of “anomalies”. • The obsolete designer must find creative ways to fabricate parts: • Focus on what is important to achieve performance • Target smaller foundries • Adapt designs/layout(s) for flexibility in die size while keeping costs within reason. MAPLD 2005/P1023