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BUSES DE DATOS CON MULTIPLEXORES Y DECODIFICADORES

BUSES DE DATOS CON MULTIPLEXORES Y DECODIFICADORES. Tri-State and Open-Collector. The Third State. Logic States: "0", "1" Don't Care/Don't Know State: "X" (must be some value in real circuit!) Third State: "Z" — high impedance — infinite resistance, no connection.

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BUSES DE DATOS CON MULTIPLEXORES Y DECODIFICADORES

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  1. BUSES DE DATOS CON MULTIPLEXORES Y DECODIFICADORES

  2. Tri-State and Open-Collector The Third State Logic States: "0", "1" Don't Care/Don't Know State: "X" (must be some value in real circuit!) Third State: "Z" — high impedance — infinite resistance, no connection Tri-state gates: output values are "0", "1", and "Z" additional input: output enable (OE) When OE is high, this gate is a non-inverting "buffer" When OE is low, it is as though the gate was disconnected from the output! This allows more than one gate to be connected to the same output wire, as long as only one has its output enabled at the same time OE 0 1 1 A X 0 1 F Z 0 1 Non-inverting buffer's timing waveform "Z" "Z"

  3. Tri-state and Open Collector Using tri-state gates to implement an economical multiplexer: When SelectInput is asserted high Input1 is connected to F When SelectInput is driven low Input0 is connected to F This is essentially a 2:1 Mux

  4. Tri-state and Open Collector Alternative Tri-state Fragment Active low tri-state enables plus inverting tri-state buffers

  5. Tri-State and Open Collector 4:1 Multiplexer, Revisited Decoder + 4 tri-state Gates

  6. Tri-State and Open Collector Open Collector another way to connect multiple gates to the same output wire gate only has the ability to pull its output low; it cannot actively drive the wire high this is done by pulling the wire up to a logic 1 voltage through a resistor OC NAND gates Wired AND: If A and B are "1", output is actively pulled low if C and D are "1", output is actively pulled low if one gate is low, the other high, then low wins if both gates are "1", the output floats, pulled high by resistor Hence, the two NAND functions are AND'd together!

  7. Tri-State and Open Collector 4:1 Multiplexer Decoder + 4 Open Collector Gates

  8. BUS BIDIRECCIONAL Registro de salida Línea bidireccional de datos D C Registro de entrada D C Sout Salida de datos Control del bus Control de entrada Sin Bus inhabilitado (alta impedancia)

  9. Read-Only Memories +5V +5V +5V +5V ROM: Two dimensional array of 1's and 0's Row is called a "word"; index is called an "address" Width of row is called bit-width or wordsize Address is input, selected word is output n 2 -1 i Word Line 0011 Dec Word Line 1010 j 0 Bit Lines 0 n-1 Address Internal Organization

  10. ROM 8 word by 4 bits F F F F 0 1 2 3 Read-Only Memories Example: Combination Logic Implementation F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' A B C address outputs

  11. Memory array n n Decoder 2 words by 2 word m bits lines m output n address lines lines Read-Only Memories

  12. Read-Only Memories 2764 EPROM 8K x 8 16K x 16 Subsystem

  13. DISEÑO Diseñar una unidad de memoria que posea las siguientes características: Un microprocesador de 20 bits de direcciones y 8 bits de datos (tipo 8088) manejará 4 bancos de memoria ROM del tipo 27256, para direccionar los 128 kbytes más altos de direcciones.

  14. 1M FFFFF H FFFFF H 128K 32K F8000 H F7FFF H 32K F0000 H EFFFF H 32K E8000 H E8000 H E7FFF H E7FFF H 32K E0000 H 128K 1FFFF H 128K 0 00000 H Mapa de memoria

  15. Mapa de decodificación de memoria  Habilitación Selección

  16. Decodificación de memoria 27256 27256 27256 27256 A0 A0 A0 A0 M E M M E M M E M A0 M E M Direc A14 A14 A14 A14 A19 32Kx8 32Kx8 32Kx8 32Kx8 D0 D0 D0 D0 D0 Datos D7 D7 D7 D7 D7 OE OE OE OE RD CS CS CS CS MICRO PROCE SADOR A17 A18 A19 DEC Y0 Y1 Y2 Y3 A15 A16

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