1 / 18

Combinational MOS Logic Circuit

Combinational MOS Logic Circuit. A. Marzuki. Topics. Static Characteristic Dynamic Characteristic Stick Diagram. Two-Input NOR Gate. V GS , load = 0 V. V OL. k = μ C ox W/L . for case either Driver are ON,. !V GS = V OH. for case both Driver are ON,. CMOS NOR GATE.

xiomara
Download Presentation

Combinational MOS Logic Circuit

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Combinational MOS Logic Circuit A. Marzuki

  2. Topics • Static Characteristic • Dynamic Characteristic • Stick Diagram

  3. Two-Input NOR Gate VGS,load = 0 V

  4. VOL k = μCox W/L for case either Driver are ON, !VGS = VOH for case both Driver are ON,

  5. CMOS NOR GATE Analysis similar to CMOS Inverter , VOL = 0 V, VOH=VDD A !VS4=VDD-VSD3 !ID3+ID4=2ID B !replace ID of B with A

  6. CMOS TG !Vout is varied. !see current direction for Source terminal indication

  7. CMOS TG EXAMPLE

  8. Complex Logic Circuits • OR by parallel-connected drivers. • AND by series-connected drivers. • Inversion by MOS circuit operation.

  9. CMOS Logic Circuit Pull up graph: vertex is drawn with area of pull down graph. Edge cross pull down graph’s edge once. Vertex represents node Pull down graph (NMOS)

  10. Equivalency PMOS Gate length increase, NMOS Gate width increase CMOS NOR Gate

  11. Discuss Example 7.2 Assuming W/L for PMOS is 15 for NMOS is 10 Answer is W/L for n is 12, while p is 12.5

  12. Dynamic Characteristics (Delay) Capacitance? Pls read chapter 6 and chapter 3. For our case, We just Use Cout i.e. the final total capacitance.

  13. Propagation Delay Chapter Six Equivalency

  14. Stick Diagram • A stick diagram is a graphical view of a layout. • Does show all components/vias (except possibly tub ties), relative placement. • Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

  15. V V DD DD Stick Diagram • Represents relative positions of transistors • Stick diagrams help plan layout quickly • Need not be to scale • Draw with color pencils or dry-erase markers Inverter NAND2 Out Out In A B GND GND

  16. Common Euler Path The Euler path is defined as an uninterrupted path that traverses each edge (branch) of the graph exactly once

  17. Comparison

  18. References • S-M. Kang and Y. Leblebici ,CMOS Digital Integrated Circuits: Analysis and Design,, 3rd edition • Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd edition, Prentice Hall, 2002.

More Related