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2/11/2003 K.Okada. 1: Today’s topic 2: Later. Run 71032 (All ERT events). 2. 1. As I understood. Timing Scan. GL1. EMC. Trigger. ERT. Cable delay (=phase). Level-1 latency. Scan the cable delay with the fixed level-1 latency. Defaults:
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2/11/2003 K.Okada 1: Today’s topic 2: Later Run 71032 (All ERT events) 2 1
As I understood Timing Scan GL1 EMC Trigger ERT Cable delay (=phase) Level-1 latency Scan the cable delay with the fixed level-1 latency. Defaults: ERT DMUX file (cable delay (subclock-clock) , level-1 latency) East : 00-50, B48C West: 00-50, B490 GTM settings (level1delay, rough delay,course delay) ERT.E : 10 , 1, 100 ERT.W : 10 , 2, 100
E3 E2 E1 E0 W3 W2 W1 W0 Sector*32+sm [/10ns] pol + delay Timing Scan #hits in 300 ppg triggers 0 is current setting. E2,E3 has less margin behind.
Time Scan Summary • Cable delay seems not functioned more than 106ns. • PbGl signal from LED doesn’t have time structure, since the width • of the LVDS signal is wide.(200ns on + 200ns off + 100ns on). • 50ns active area imples EMCal timming is well adjusted to the center • of the global timing. • The default value of the EAST arm is close to the border line. • Action • Add 10ns delay to the EAST EMCal DMUX files. (Feb 9, 0:26) • (00-50 28-50) • It needs to check the EMCal-RICH coincidence.
Run71369 hit distribution of electron trigger (mask=0xc00) RICH occupancy seems fine.
Run71369 2x2triggered events (mask=0x30) EMCal E2,E3 occupancy seems good
Summary The EMCal timing had been inappropriate point. It was added 10ns and seems fine for both EMCal and electron trigger. How do we know the good timing for RICH?
