Computer Systems Organization & Architecture Chapter 1 Part 3 Combinational Logic

1. Computer Systems Organization & Architecture Chapter 1 Part 3 Combinational Logic

2. Logic Array: structured networks that can be configured to produce specific forms of logic expressions Example: may be designed to accept inputs and produce specific miniterms as outputs Classify by either the function they perform or the form of the Boolean term they produce Logic Arrays

3. AND array Accepts input variables and produces miniterms at the output Logic Arrays

4. Uncommitted logic arrays Provides gates and wires, but does not connect them Lack of black dots indicates no connections present Logic Arrays Can program the array by specifying input connections

5. Programmable Logic Arrays (PLAs) Uncommitted logic array Can “burn” in connections to program the circuit Much used in modern digital design. Logic Arrays

6. OR array Same as AND array except use OR gates Logic Arrays

7. OR array Example OR PLA with connections Logic Arrays

8. SOP PLAs Cascade two logic arrays The AND plane produces the miniterms Logic Arrays

9. POS PLAs Cascade two logic arrays The OR-plane produces the maxiterms Logic Arrays

10. Example: AND-OR array Step 2: figure out the sums using the OR gates: Logic Arrays Step 1: figure out the miniterms: ABC, A’B’C’, etc.

11. Shorthand notation. Below is same PLA as previous slide. Gate input replaced by a single line that represents several independent lines. Connections are still dots, but dots connect two individual lines, not entire group. The number of inputs to a gate is equal to the number of connection dots in the input line. Logic Arrays

12. Shorthand notation. Below is same PLA as previous slide. Logic Arrays

13. Example: OR-AND array Step 2: figure out the products using the AND gates: Logic Arrays Step 1: figure out the maxiterms: A+B+C, A’+B’+C’, etc.

14. Many companies produce commercial PLAs. Easy to program Recent products allow designer to design and test very complex systems. Often used for fast prototyping. Programmable logic arrays (PALs). Same as PLAs except that only the And array may be programmed; the Or array is fixed. PALs have more room for input/outputs, gates, etc. because programmable logic for the Or array takes lots of room. PALs are easier to program and are faster. Programmable Logic Arrays

15. Field-programmable gate arrays (FPGA) Commercial devices PLAs that can be programmed by users using special equipment Used to implement highly complex logic networks. Drawbacks Resulting circuit probably not very efficient use of gates Some gates in the PLA will be unused. Design will not fastest implementation. Do not minimize the output functions Programmable Logic Arrays

16. A multiplexer is a selector. Chooses one of its inputs and passes it through to its output Next slide: a 4-to-1 multiplexer Four binary data values passed to the inputs of the MUX Two select signals to MUX. These determine which input is passed to the output An enable line will turn the MUX on/off Multiplexers (Mux)

17. Multiplexer

18. Active high MUX

19. Active Low MUX

20. Can develop larger MUX. Problem: fan-in limits Better: cascade Example: construct a 4-to-1 MUX out of three 2-to-1 MUX Larger MUX

21. Technique: use hierarchies of smaller components Example: creating 4x1 mux from 2x1 mux Will create a 2-level mux tree First level takes the initial inputs The results from the first level are fed into the second level Larger MUX

22. Technique Divide the truth table into equal sections Number of sections given by type of second-level MUX If the second-level MUX is 2x1 then need 2 sections in the TT Hierarchy Approach Section 1 Section 2

23. Technique Connect the outputs corresponding to individual sections of the TT to the data lines of the individual first-level MUXs Hierarchy Approach Input 0 Outputs from Section 1 of Truth Table 2x1 Mux Input 1 Outputs from Section 2 of Truth Table 2x1 Mux Input 2 Input 3

24. Technique Connect the outputs of the first-level MUXs to the data lines of the second-level MUX following the order of the sections Hierarchy Approach Input 0 2x1 Mux Input 1 2x1 Mux 2x1 Mux Input 2 Input 3

25. Technique Connect the least significant selectors, those which are rightmost in the TT, to the first-level select lines Connect the remaining variables to the select lines of the second-level of the tree Hierarchy Approach Input 0 2x1 Mux Input 1 2x1 Mux 2x1 Mux Input 2 Input 3 S1 S0

26. 4-to-1 MUX made from 2-to-1 MUXs

27. Alternative design technique. Can double the size of the truth table that a given MUX can handle. Folding

28. A decoder: Accepts a Boolean value (number) and activates the corresponding output line All other lines are deactivated For n inputs there are 2n output lines Each possible input value corresponds to an output line Next slide: a 2-to-4 decoder For inputs S1S2 = 00, 01, 10, 11 corresponding activated outputs are lines 0, 1, 2, and 3. Decoders

29. 2-to-4 Decoder Can have active high or active low enables.

30. 2-to-4 decoder with active high enable

31. 2-to-4 decoder with active low enable

32. An encoder: For 2n inputs there are n output lines Outputs the Boolean value corresponding to the input line number There is a special output line V that indicates whether any input lines are active. Encoders

33. Next slide: a 4-to-2 encoder For inputs 0, 1, 2, and 3 the output values are S1S2 = 00, 01, 10, 11 Output values are 00 if input line 0 is active or if none of the inputs is active. The V value distinguishes between these. If more than one input line is active, outputs value will be wrong. We will fix this with a priority encoder. Encoders

34. 4-to-2 encoder

35. 4-to-2 encoder, high enable

36. 4-to-2 encoder, low enable

37. Works like a normal encoder If more than one input is active, output is set to highest active input. If input lines 0, 1, and 3 are active, output set to 11 Next two slides give two possible implementations of a 4-to-2 priority encoder First disables an input if a higher numbered input is already active Second modifies circuit to give priority. Priority Encoders

38. Priority Encoder, version 1

39. Priority Encoder, version 2 • The circuit eliminates unnecessary priorities • Example: S1 is set if input 2 is high, even if input 3 is also high since it would also be set for input 3.

40. Compares two n-bit binary values to determine which is greater or if they are equal Next slide: 1-bit comparator Uses a XNOR gate (exclusive NOR) Comparators

41. 1-bit Comparator

42. Compare most significant bit, then next bit, etc. Must modify previous circuit to include info from previous comparisons If X = Yin line is set, then circuit for next bit is same as before If X > Yin or X < If X = Yin line is set, then circuit for next bit is same as before If X > Yin or X < Yin are active, must pass these values through Next slide: modified 1-bit comparator Following slide: n-bit comparator Multi-bit Comparators

43. 1-bit comparator using previous results

44. n-bit comparator