Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Mei Kim Ding, and Richard B. Brown

1. Top-Down and Bottom-Up Approaches to Stable Clock Synthesis LecturerMichael S. McCorquodaleAuthorsMichael S. McCorquodale, Mei Kim Ding, and Richard B. Brown Solid State Electronics Laboratory Center for Wireless Integrated Microsystems (WIMS) Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor, MI USA 48109-2122 International Conference on Electronic Circuits and Systems, Sharjah, U.A.E., 2003

2. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Lecture Overview • Overview of Clock Synthesis • Effects of Frequency Translation on Frequency Stability • Top-Down and Bottom-Up Synthesis • Application • Design and Simulation • Results • Conclusions and Future Work

3. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Clock Synthesis • The clock is arguably the most significant signal in any synchronous system • Harmonic quartz XTAL reference + PLL is the ubiquitous approach • High accuracy and stability • Broad range of output frequencies • Drawbacks • Discrete components required (not monolithic) • PLL power and area • Systemic short-term stability degradation (to be presented) • Challenges in developing an alternative (possibly monolithic) approach • Accuracy and stability • Monolithic reference (typically low-Q)

4. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Period Jitter: s of the position of the next edge relative to the ideal Ideal Period Period Jitter tk tk+1 Phase Noise: Power relative to fundamental at some offset fm P fm f fo Short-Term Frequency Stability Metrics

5. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Phase and frequency are related by a linear operator: Frequency mult./div. results in phase noise mult./div.: Using narrowband FM approximation: Linear freq. translation results in quadratic change in noise power Frequency Multiplication and Division

6. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions The SSB phase noise PSD can be represented by a Lorentzian function: Which can be approximated for: 20dB/dec fm Converting Phase Noise to Period Jitter Using the above: • Typically pfo2c called corner or line width: select fm above the corner and below fo • Lorentzian implies absence of flicker noise (slope must be 20dB/dec)

7. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Using phase noise conversion expression, determine jitter: Considering fractional, or ppm, jitter: Frequency translation also enhances and degrades jitter Frequency Translation and Jitter

8. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Leeson Phase Noise Model Relationship with Quality-Factor • Leeson model: Q-factor quadratically related to phase noise • Q-factor is one of the most significant metrics indicating stability • Typical quartz XTAL Q on the order of 10,000 • Frequency translation also quadratically related to phase noise • Consider effective Q-factor modification due to freq. translation • If NdivNmult > Qmult/Qdiv then divided signal more stable • Assumption: oscillator power and noise factor are the same • Nmult for XTAL+ PLL up to 4096: high-Q, but large degradation

9. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Frequency Translation Summary

10. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions fref PFD CP LPF vctrl Nfref ÷N A Bottom-Up Approach Quartz XTAL reference oscillator + PLL The signal that actually drives the processor is a frequency multiplied (and degraded) image of the reference

11. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions ÷N fref frefN A Top-Down Approach A harmonic LC (and monolithic) RF reference The signal that actually drives the processor is a frequency divided (and enhanced) image of the reference LC reference also provides good accuracy as compared to ring or relaxation approach

12. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Application Test Bench • Intel SA-1110 • 3.6864MHz XTAL reference + PLL • ~200MHz max output frequency • Bottom-up Approach • 3.125MHz XTAL, Q = 10,000 • Output = 200MHz, N = 64 • Top-down Approach • 3.2GHz reference, Q = 10 • Output = 200MHz, N = 16 All transistor design with TSMC 0.18 MM/RF

13. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions XTAL lumped parameter model Pierce Bottom-Up XTAL Reference OSC 3.125MHz XTAL reference 50 1 500k 30 1 7p 389m 4.79f 900 30p 30p Requires off-chip XTAL + 2 capacitors + 1 resistor

14. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions bias 2 0.18 4 0.18 2 0.18 4 0.18 2 0.18 4 0.18 from last stage from last stage Ring Bottom-Up VCO 20-stage 200MHz current-starved ring VCO

15. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions A Bottom-Up System Remainder of PLL modeled with Verilog-A fref PFD CP LPF vctrl Nfref ÷N

16. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions 36 0.18 bias 100 0.18 100 0.18 2nH 950fF 40 0.18 40 0.18 LC Top-Down Reference OSC 3.2GHz monolithic RF LC reference oscillator

17. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions 3.2GHz D D D D Q Q Q Q + DFF DFF DFF DFF AMP - 200MHz Q Q Q Q Top-Down System Implementation Entire system designed at the device level Each feedback flip-flop divides frequency by two

18. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Design and Simulation • Bottom-up Approach • Phase noise for reference OSC and VCO simulated at device level • Device-level results modeled with Verilog-A • Entire PLL modeled with phase domain approach using Verilog-A • Top-down Approach • Entire system simulated at the device level

19. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Bottom-Up Phase Noise Performance

20. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Bounding PLL Phase Noise

21. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Top-Down Phase Noise Performance

22. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Performance Comparison

23. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Conclusions and Future Work • Frequency multiplication degrades short term stability and effectively reduces reference oscillator Q • Frequency division enhances short-term stability and effectively increases reference oscillator Q • Bottom-up approach requires reference XTAL OSC + PLL while top-down approach requires only reference OSC + divider • For a common application, top-down approach provides comparable frequency stability to bottom-up approach, while being substantially simpler to implement • Top-down approach facilitates monolithic integration • Such a clock synthesis system has been developed and will be reported in the near future • More sophisticated top-down architectures will be explored

24. Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Conclusions and Future Work Questions?