Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI Design

1. Spezielle Anwendungen des VLSI – EntwurfsApplied VLSI Design Jacob Maxa Results of Phase 4: Chip Layout 10.01.2013 Institute MD, University of Rostock

2. Challenge • Create a fully working chip layout • Redo the same task with additional I/O pads • Ideas • Optimize VHDL/Verilog source and netlist • Shrink internal bit width from 10 to 8 • Minimize needed core area • Rectangular layout • Shorten wires as good as possible (high effort routing) • Create a special clock mesh • H-Tree form • GND guard shield to avoid crosstalk • Optimize for DFM • Antenna fixing

3. Routing • Global Routing • Generate global routing mesh • Detail Route • Connect pins with it corresponds and the global mesh • Post Route Optimization • Fix violated design rules • Via – combine/split vias to fit DRC • Wire – shorten wires • Fix Antenna • Timing Driven • Optimize to low wire delay • SI (signal integrity) Driven

4. Clock Mesh • After cell placement • Uses clock buffer • Fill free spaces between cells • H-Tree from • Double sided shield with GND net • M3 & M4

5. Timings • Adding timing constraints to improve optimizations • Repeat for highest frequency • Perform design optimization • Reroute wires • Density: 90.799% +--------------------+---------+---------+---------+---------+---------+---------+ | Hold mode | all | reg2reg | in2reg | reg2out | in2out | clkgate | +--------------------+---------+---------+---------+---------+---------+---------+ | WNS (ns):| 0.010 | 0.048 | 0.010 | N/A | N/A | N/A | | TNS (ns):| 0.000 | 0.000 | 0.000 | N/A | N/A | N/A | | Violating Paths:| 0 | 0 | 0 | N/A | N/A | N/A | | All Paths:| 296 | 141 | 155 | N/A | N/A | N/A | +--------------------+---------+---------+---------+---------+---------+---------+ +--------------------+---------+---------+---------+---------+---------+---------+ | Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate | +--------------------+---------+---------+---------+---------+---------+---------+ | WNS (ns):| 0.047 | 0.047 | 1.644 | N/A | N/A | N/A | | TNS (ns):| 0.000 | 0.000 | 0.000 | N/A | N/A | N/A | | Violating Paths:| 0 | 0 | 0 | N/A | N/A | N/A | | All Paths:| 296 | 141 | 155 | N/A | N/A | N/A | +--------------------+---------+---------+---------+---------+---------+---------+

6. Results (1/3)

7. Results (2/3) • Power requirements • 22,38 % clock network • 57,64 % registers • 19,98% combinational

8. Results (3/3) After Optimization Before Optimization

9. Layout with Pads • Power requirements • 99,29 % I/O Pads • 0,14 % clock network • 0,45 % registers • 0,12 % combinational

10. End • Thanks for your attention! • Questions?

11. Metric