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Lab Lectures

Lab Lectures. Preparation for ECEn 320 Lab Exercises. Suggestions for a Productive Lab Experience. Design Start early, come to lab prepared. Understand the assignment before you begin to code VHDL Design from your drawings-- have your block diagram in front of you when you write the VHDL

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Lab Lectures

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  1. Lab Lectures Preparation for ECEn 320 Lab Exercises BYU ECEn 320

  2. Suggestions for a Productive Lab Experience • Design • Start early, come to lab prepared. • Understand the assignment before you begin to code VHDL • Design from your drawings-- have your block diagram in front of you when you write the VHDL • Use good VHDL coding practices. Make your VHDL code legible. • Comment your code. • Simulation • Debug using the simulator, not the board • When you ask a TA “What’s wrong with my design?” -- be prepared to show him a simulation of the current design • Save your simulation stimulus, or use do files. You don’t have to rebuild the simulation from scratch every time. • Working with the TAs • Ask proper questions: “My design doesn’t work.” is not a question. • Don’t expect them to hold your hands, or read to you. • Have the TAs sign your pass-off sheet when you have passed-off. BYU ECEn 320

  3. Lab 1 : Seven-Segment Display Driver Displaying a hexadecimal number BYU ECEn 320

  4. A1 Expansion Connector A2 Expansion Connector VGA B1 Expansion Connector Power Serial PS2 Get to Know Your Spartan 3 Board BYU ECEn 320

  5. Spartan 3 Board BYU ECEn 320

  6. A1 Expansion Connector A2 Expansion Connector VGA B1 Expansion Connector Power Serial PS2 Lab 1 Specification Display value on 8 switches on the seven-segment display.Leave top two digits blank. BYU ECEn 320

  7. 7-Segment DisplayonSpartan 3 Board Leave Blank 8-bit Switch Value, in Hexadecimal BYU ECEn 320

  8. Seven-Segment Display • Seven “segment” input signals (A-G) plus a “decimal-point” input signal (DP) control which segments are lit. • Shared by all four digits • Four “anode” control input signals control which digit is lit. Board schematic of the seven-segment display circuit Seven-Segment Display Module BYU ECEn 320

  9. Seven-Segment Display • The four anode control inputs are time-multiplexed (asserted at different time intervals, taking turns) to display data on all four characters. • Present the value to be displayed on the segment control inputs and select the specified character by driving the associated anode control signal Low. • Through persistence of vision, the human brain perceives that all four characters appear simultaneously, similar to the way the brain perceives a TV display. BYU ECEn 320

  10. Seven-Segment Display Timing Note:Anode and Segment signals are all LOW asserted. Pattern repeats BYU ECEn 320

  11. Seven-Segment Decoder Logic Note: Segment signals are LOW asserted. Switch value (4-bits) BYU ECEn 320

  12. FPGA Pins - Seven Segment Display BYU ECEn 320

  13. Switches • When in the UP or ON position, a switch connects the FPGA pin to VCCO, a logic High. • When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low. • The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry, although such circuitry could easily be added to the FPGA design. (We will do this in lab 3). • A 4.7KΩ series resistor provides nominal input protection. BYU ECEn 320

  14. Switches BYU ECEn 320

  15. Clock and Reset Circuits • The board has a dedicated 50 MHz clock oscillator source. • Use the 50 MHz clock frequency along with the FPGA’s Digital Clock Managers (DCMs) to create the internal clock. • The left-most button, BTN3, is the default User Reset pin. • BTN3 electrically behaves identically to the other push buttons, however is used as a reset by convention. BYU ECEn 320

  16. Advantages of Using the DCM • DCM = Digital Clock Manager. (Includes the DLL). The Spartan 3 includes four DCMs that you can use. • Filters the input clock to provide a stable internal clock. • Guarantees 50% duty cycle internal clock. • Provides a signal “locked” that tells when clock is stable and operating. • Can be used to provide other related clocks: • A clock at twice the input clock frequency. • Clocks at divided rates. BYU ECEn 320

  17. Clock and Reset Generator Circuit FPGA Pins clk Internal Signals clkfb 50 Mhz IBUFG clk0 (50 Mhz, 50% Duty Cycle) clk clk_in clkin clk0 clkbuf BUFG locked DLL Delay Lock Loop inDigital Clock Manager Clkdiv(23 downto 0) clkdiv 24-bitCounter rst_in Input Clock Divider rst set set set set (internal reset) Reset Synchronizer A clean clock is very important. This circuit is the best way to generate a good clean clock in the FPGA. Never gate the clock. BYU ECEn 320

  18. System Level Block Diagram Clock Pin 50 MHz ClockGenerator 4 MS bits 4 LS bits clk Multiplexer Decoder Clock DivideCounter digit select 4 bits Seven-Segment Encoder blank (See question 3.) BYU ECEn 320

  19. Lab 1 Procedure • Design a circuit to display the 8-bit switch value on the two digits of the seven segment display. • Use the suggested clock/reset generator circuit. • Simulate your VHDL file with the Aldec tool. • Synthesize your design and download your bit file to the board. • Verify that your circuit works as predicted by simulation. • Answer the questions. BYU ECEn 320

  20. Lab 1 Questions • The seven-segment display interface has 12 input pins: 7 segment pins, 1 DP pin, and 4 anode pins. Why does the display manufacturer time-multiplex the display, instead of providing segment and DP pins for each digit ? How many pins did they save ? How many pins would an 8-digit display require if you have anode pins, and how many pins are needed if you don’t have anode pins ? • The input frequency to the clock divider is 50 MHz. Make a table of the frequencies of each of the 24 clock divider output bits, clkdiv(23 downto 0) where clkdiv(0) is the LSB and clkdiv(23) is the MSB. • If you scan the digits too slow, they will appear to flicker. If you scan the digits too fast, they will be dim. What bits of the clock divider did you decode to drive the anodes of the seven-segment display ? What is the corresponding scanning frequency ? How did you decide what clock divider bits to use ? • When a switch is in the high position, what is the resistance between VCCO power and the FPGA input pin ? What is the resistance between Ground and the FPGA input pin when the switch is in the low position ? • The reset synchronizer circuit given here guarantees that the internal reset is on at least how many clock cycles ? Does the circuit guarantee that internal reset signal rises and falls synchronous to the clock ? BYU ECEn 320

  21. Lab 1 Objectives • Learn to use the Aldec simulation tool. • Learn to use the Xilinx synthesis and implementation tools. • Design a working VHDL circuit. • Learn how to properly generate a clock and reset • Learn how to properly divide a clock • Learn how to properly drive the seven-segment display. • Learn how to download your design to the board. BYU ECEn 320

  22. Lab 2 : UART Transmitting and Receiving Serial Data BYU ECEn 320

  23. The ABC’s of Serial Ports • UART = Universal Asynchronous Receiver/Transmitter • TX = Transmitter • RX = Receiver • TD = Transmit Data (Data output) • RD = Receive Data (Data input) • RTS = Request to Send (Flow control output) • CTS = Clear to Send (Flow control input) • Half Duplex – transmits one direction at a time (mostly obsolete now) • Full Duplex – transmits both directions at the same time • RTS/CTS Flow control for full duplex serial ports : • RX assert RTS when it is ready to receive • TX waits for CTS before transmitting BYU ECEn 320

  24. Serial Port Devices The following is a list of various hardware components that use Serial Ports : • Mouse - One of the most commonly used devices for serial ports. • Modem - Used commonly with older computers. • Network - One of the original uses of the serial port, which allowed two computers to connect together and transfer large files between the two. • Printer - Mostly used with older printers only. • ASCII Terminal (TTY) - Like the Hyperterm interface. BYU ECEn 320

  25. Hooking Up Two Serial Ports Full Duplex TD RD RTS CTS GND TD RD RTS CTS GND BYU ECEn 320

  26. Serial PortonSpartan 3 Board DCD DSR RXD RTS TXD CTS DTR RI BYU ECEn 320

  27. Serial Communication Format • Data is transmitted sequentially, one bit at a time. • To inform the receiver that a new byte is arriving, a “start bit” (a zero) is sent first. A start bit can start at any time. • Then the data is transmitted, LSB (least significant bit) first, and MSB (most significant bit) last. • At the end, one or two “stop bits” (ones) are transmitted. • A frame consist of : • 1 start bit (a zero) • 7 or 8 data bits LSB (least significant bit) first • 1 optional parity bit • 1 or 2 stop bits (ones) • Between transmissions, the transmitter transmits a high. • The bit time is determined by the baud rate which is given in units of BPS (bits per second). • Transmitter and receiver do not share a clock (hence the asynchronous nature). BYU ECEn 320

  28. Serial Frame http://www.atmel.com/dyn/resources/prod_documents/DOC0941.PDF http://www.wcscnet.com/Tutorials/SerialComm/Page1.htm BYU ECEn 320

  29. Transmitting BYU ECEn 320

  30. Receiving 1.5 bit time 1.5 bit time BYU ECEn 320

  31. Receiver Sample Timing Slightly Faster Baud Rate Exact Baud Rate Slightly Slower Baud Rate 1BitTime 1.5Bit Time BYU ECEn 320

  32. Lab 2, Part 1UART Transmitter BYU ECEn 320

  33. A1 Expansion Connector A2 Expansion Connector VGA B1 Expansion Connector Power Serial PS2 Lab 2, Part 1 Specification Send ASCII value on 8 toggle switches to serial port for display on screen when button 1 is pressed. BYU ECEn 320

  34. Top Level System Block Diagram Clock/Reset Generator Switch and Button InterfaceButton Debouncer Two Entities: tx_test - top level file to test the transmitter tx - The transmitter itself, which is instantiated in the body of tx_test You will need the transmitter (tx) for Part 3. of this lab. tx_test tx Transmitter BYU ECEn 320

  35. Transmitter Tester (tx_test)Block Diagram tx Clock/Reset Generator clk (50 MHz) rst clk_in Debounce Circuit send_character button serial_out tx_complete (open, or LED) txd 8 data_in switch(7 downto 0) ctsn BYU ECEn 320

  36. Clock and Reset Generator Circuit FPGA Pins clk Internal Signals clkfb 50 Mhz IBUFG (50 Mhz, 50% Duty Cycle) clk_in clk0 clk clkin clk0 clkbuf BUFG locked DLL Delay Lock Loop inDigital Clock Manager rst set set set set (internal reset) Reset Synchronizer No external reset button, ‘rst’ is internally generated. BYU ECEn 320

  37. Transmitter (tx) Block Diagram clk rst SerialGenerator data_in serial_out 8 stopBit bit_sel 3 startBit FSM clk rst BitCounter send_character clrCount ctsn bit7 clkrst incCount BitTimer clk rst tx_complete tx_bit clrTimer BYU ECEn 320

  38. Bit Timer - Transmitter Clocking • Everything is clocked on same global clock (clk) • Global clock is 50MHz • The Bit Timer controls the timing of bits coming out of the serial port. • Bit Timer needs to create timing pulse at rate of 19,200Hz • That is the baud rate of our serial port • Divide factor = 50,000,000/19,200 = 2604.1666… • We will use 2604 cycles/pulse BYU ECEn 320

  39. Transmitter Bit Timer • Is a counter • Can be cleared, otherwise increments up to 2603 and rolls over • Signal tx_bit is asserted when it reaches 2603 clk tx_bit 2604 cycles state serial_out “one bit” BYU ECEn 320

  40. Hints for Creating the Bit Timer signal timer : std_logic_vector(11 downto 0);signal tx_bit : std_logic; … process(clk)begin -- create bit timer counter -- clrTimer and rst are synchronous clears -- wraps to 0 after counting to 2603 (A2B hex)end process; -- combinational tx_bit <= ‘1’ when timer = X”A2B” else ‘0’; 2603 (decimal) = A2B (hex) = 101000101011 (binary) BYU ECEn 320

  41. Transmitter Bit Counter • Is a counter • cleared synchronously with clr_count • incremented with inc_count • counts from 0 to 7 and then wraps to 0 • It counts how many bits have been transmitted • The count is a 3-bit bit_sel output that selects which data bit is to be sent next. • bit7 tells FSM when its current count=7(Means the last bit is being transmitted) BYU ECEn 320

  42. Serial Generator • Outputs a ‘0’ when startBit is high • Outputs a ‘1’ when stopBit is high • Outputs selected data bit fromdata_inotherwise • Output of combination logic should be registered using a flip-flop to ensure clean serial_out signal • The Flip-Flop will remove any transient glitchs. • IFL + register design (MUX + gates + FF) • Synthesizer will infer synchronous set/clear on FF from startBit and stopBit if possible CombinationalLogic BYU ECEn 320

  43. Transmitter FSM • FSM handshakes with outside world send_character tx_complete data_in … serial_out Data transmission here… Start bit Stop bit BYU ECEn 320

  44. Transmitter FSM • Controls start/stop bits to Serial Generator • Controls clearing/increment of Bit Counter • Controls clearing of Bit Timer • Reacts to Bit Counter and Bit Timer BYU ECEn 320

  45. Transmitter FSM send_character + ctsn send_character rst send_character IDLE RETRN stopBittx_complete send_character • ctsn stopBitclrCountclrTimer START tx_bit tx_bit startBit tx_bit stopBit RUN STOP tx_bit tx_bit • bit7 tx_bit tx_bit • bit7 / incCount We will give you the state machine for this lab, for the next lab you will design your own! BYU ECEn 320

  46. Output Glitching • Signal serial_out should be clean (not glitch) • If it is register output – it will be clean (in tx serial generator) • Signal tx_complete should also be clean • Run it through flip flop after it leaves FSM (in tx) • Signal send_character should be clean • Filter the push button through a “button debouncer” (in tx_test) • What about other signals… ? • Since they drive other circuitry in the same clock domain: don’t care BYU ECEn 320

  47. Button Debounce Circuit button settle time is typically around 10 msec switch settle time switch settle time buttoninput DebounceLogic output A digital equivalent of a low pass filter BYU ECEn 320

  48. Debounce Circuit Timer/Clock Divider clk en_sample Tsample > Tsettle D Q en bouncy debounced clk en_sample Tsample bouncy Tsettle debounced BYU ECEn 320

  49. Suggested Incremental Design Process • Create file tx.vhd with all its ports and internal signals • Use port names from drawing – other circuitry expects these names • Design Bit Timer as a process in it • Simulate it • Then, simulate everything else with it having MUCH SMALLER terminal count (how about 4 instead of 2604?) • Add Bit Counter process • Simulate everything so far • Add Serial Generator process • Simulate everything so far • Add FSM processes • Simulate entire circuit • Don’t forget to change timer terminal count back before synthesizing… BYU ECEn 320

  50. Three Testing Options • Add Aldec simulators to your inputs • Create a simulator for each input using “Add Simulator” in Aldec • Like you learned in the tutorial • Write a ‘do’ file • Create a file containing simulator commands such as force statements using the simulator’s script language • Run this script to run your simulation • Dr. Nelson’s favorite method • Write a test bench • Create a test bench entity (no inputs or outputs) • Write VHDL in the test bench architecture to driveyour unit-under-test (UUT) TestBench UUT VHDL BYU ECEn 320

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