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Reaching Agreement in the Presence of Faults

Reaching Agreement in the Presence of Faults. M. Pease, R. Shostak, and L. Lamport SRI International, Menlo Park, California. Presented by: Prabhjot Mall. Abstract.

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Reaching Agreement in the Presence of Faults

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  1. Reaching Agreement in the Presence of Faults M. Pease, R. Shostak, and L. Lamport SRI International, Menlo Park, California Presented by: Prabhjot Mall

  2. Abstract The problem concerns a set of isolated processors, some unknown subset of which may be faulty. Each non-faulty processor has a private value that must be communicated to every other non-faulty processor.

  3. The Problem The value inferred for a non-faulty processor must be the processor’s private value and the value inferred for a faulty processor must be consistent with the corresponding value inferred by each other non-faulty processor.

  4. Claim The given problem is only solvable for n ≥ 3m +1, where m is the number of faulty processors and n is the total number of processors.

  5. Interactive Consistency Compute a vector of values for every processor, such that: • The non-faulty processors compute the exact same vector • The element of this vector corresponding to a given non-faulty processor is the private value of that processor.

  6. Interactive Consistency The algorithm guarantees Interactive Consistency since it allows the non-faulty processors to come to a consistent view of all processors. The computed vector is called the Interactive Consistency Vector.

  7. The Single-Fault Casem=1, n=4 The procedure consists of an exchange of messages, followed by the computation of the interactive consistency vector on the basis of the results of the exchange. Two Rounds of exchange are required. In the first round the processors exchange their private values and in the second round they exchange the results obtained in the first round.

  8. The Single-Fault Case [V1] [V2] [V3] [V5] V1 V2 V3 V4 Faulty Non Faulty

  9. The Single-Fault Case [V1] [V2] [V3] [V6] V1 V2 V3 V4 Faulty Non Faulty

  10. The Single-Fault Case V1 V2 [V1] [V2] [V3] [V4] V3 V4 Faulty Non Faulty

  11. The Single-Fault Case [V1] [V2] [V3] [V5] [V1] [V2] [V3] [V6] V1 V2 [V1] [V2] [V3] [V4] [V1] [V2] [V3] [V4] V3 V4 Faulty Non Faulty

  12. The Single-Fault Case [V1] [V2] [V3] [NIL] [V1] [V2] [V3] [V6] V1 V2 [V1] [V2] [V3] [V4] [V1] [V2] [V3] [V4] V3 V4 Faulty Non Faulty

  13. The Single-Fault Case [V1] [V2] [V3] [V5] [V1] [V2] [V3] [NIL] V1 V2 [V1] [V2] [V3] [V6] V3 V4 [V1] [V2] [V3] [V4] Faulty Non Faulty

  14. The Single-Fault Case [V1] [V2] [V3] [V5] [V1] [V2] [V3] [V6] V1 V2 [V1] [V2] [V3] [V4] [V1] [V2] [V3] [NIL] V3 V4 Faulty Non Faulty

  15. The Single-Fault Case [V1] [V2] [V3] [NIL] [V1] [V2] [V3] [NIL] V1 V2 [V1] [V2] [V3] [NIL] [V1] [V2] [V3] [NIL] V3 V4 Faulty Non Faulty

  16. Procedure for n≥3m+1 For 1 faulty processor  2 rounds of communication For m faulty processors  m+1 rounds of communication P: Set of processors V: Set of values k≥1: k-level scenario  mapping from a set of non-empty strings {p1,p2,p3,…pn} over P of length k+1, to V Example: For a k-level scenario σ and string w=p1p2…pn σ(w) = the value of pn that pn tells p(n-1) … which p2 tells p1

  17. Procedure for n≥3m+1 For an arbitrary processor p, a non faulty processor q and a string w σ(pqw) = σ(qw) The message a processor p receives in a scenario σ are given by the restriction σp of σ to strings beginning with p.

  18. Procedure for n≥3m+1 For some subset Q of P size(Q) ≥ (n+m)/2 If σp (pwq) = v for each string w over Q p records the value of q as v. Otherwise, the algorithm for m-1, n-1 is recursively applied with P replaced by P-{q} and σp(pwq) by σp(pw). If at least (n+m)/2 of the n-1 elements in the vector obtained by the recursive call agree p records the value of q as v, otherwise it records NIL.

  19. Two Faulty Processors V2 [v1] [v2] [v3] [v9] [v5] [v8] [v7] V3 V1 V4 V6 V7 V5 Faulty Non Faulty

  20. Two Faulty Processors [v1] [v2] [v3] [v8] [v5] [v0] [v7] V2 [v1] [v2] [v3] [NIL] [v5] [NIL] [v7] [v1] [v2] [v3] [v4] [v5] [v6] [v7] V3 V1 [v1] [v2] [v3] [v4] [v5] [NIL] [v7] V4 V6 [v1] [v2] [v3] [v8] [v5] [v0] [v7] [v1] [v2] [v3] [v8] [v5] [v0] [v7] V5 V7 Faulty Non Faulty

  21. Questions? Aren’t you glad this is over???

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