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R & D Work at SMU

R & D Work at SMU. The Test of the GOL chip. First test on the SoS driver chip and the submission of a dedicated test chip for radiation tests. Test results of the GSE laser and a 10 GHz VCSEL . The SMU group: Wickham Chen, Ping Gui, Andy T. Liu, Ryszard Stroynowski,

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R & D Work at SMU

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  1. R & D Work at SMU The Test of the GOL chip. First test on the SoS driver chip and the submission of a dedicated test chip for radiation tests. Test results of the GSE laser and a 10 GHz VCSEL . The SMU group: Wickham Chen, Ping Gui, Andy T. Liu, Ryszard Stroynowski, Annie C. Xiang, John C. Yang, PeiQing Zhu,, Juheng Zhang, Jingbo Ye GOL + SoS

  2. 1 to 2 Gbps serialisers, why GOL GOL 1.6 Gbps G-Link 1.25 Gbps TLK2501 2.5 Gbps Rad-soft 360 mW Rad-hard by design, 400 mW LD driver included Rad-hard Bi-polar, 2.5 W 23.2×17.2mm2×2.7mm Price: $50/pcs 12.2×12.2mm2×1mm 13×13mm2×1.7mm Price: $15/pcs GOL + SoS

  3. GOL overview • GOL overview: • Transmission speed • Fast: 1.6Gbps, 32 bit@40MHz • Slow: 0.8Gbps, 16 bit@40MHz • Encoding scheme • CIMT (ex: HDMP-1024) • 8B/10B (ex: TLK2501) • Program interface • I2C • JTAG • Driver • Internal laser driver (bias: 1 mA to 55 mA in 0.4 mA steps) • 50ohm line driver, minimum 780 mV differential. • Good for VCSEL and Edge Emitter. Package: 144 pin fpBGA with 1 mm solder-ball pitch. Dimensions: 13 mm sides, 1.68 mm tall. GOL + SoS

  4. GOL architecture GOL + SoS

  5. Previous tests [ Ref. GOL CERN website ] • Total dose effect: 10Mrad (x-ray, 10 KeV peak) at a dose rate of 10.06 Krad(SiO2)/min. No current increase after the irradiation. • SEU: 60 MeV proton, fluence of 3×1012 p/cm2 at a flux of3×108p/cm2sec. No SEU was observed. Requirements: 10 to 100 Mrad and 1015 to 1016p/cm2 fluence. • BER tests in lab: better than 1.3×10-14. • Power consumption: 400 mW. GOL + SoS

  6. Test of the GOL chip We plan: • A complete chip characterizing according to the IEEE Gigabit Ethernet standard. This includes rise/fall times, eye mask test, jitter studies (DJ and RJ at all 4 testing points of the link system, jitter transfer of the GOL), optical power margin (again in the link system). We did this for the G-Link for the LAr optical link. Agilent didn’t provide it in the data sheet. • The PLL lock range. • Probe the total dose limit to see if it reaches 100 Mrad. Measure SEUs at different flux levels, using 200 MeV proton beams. • Gain experience of using this chip, should it be suitable to inner detector upgrade. GOL + SoS

  7. System block diagram for in lab test Pattern/clock generator with jitter input TP1 TP2 TP3 PC interface TP4 GOL + SoS

  8. System block diagram for irradiation test Control Room 37 m away 2 m away from the beam In the beam RS232 Freq. Counter GPIB Prog. V. Source GPIB Picoammeter Test chip Carrier Board 1 PC Switch Board Flux Test Chip Carrier Board 2 USB DIO Card FPGA Board GOL Board 1 This design is still in progress and is changing on daily basis. TTLLVDS TLK Rx GOL Board 2 TTLLVDS TLK Rx GPIB Power Supply Board DMM GOL + SoS

  9. The schedule 10/1/05 System design 1 month We are here 11/1/05 Schematic capture 1 month 12/1/05 PCB layout 1 month FPGA code 1.5 month Labview code 1 month 1/15/05 Board assembly 3 wk 2/15/06 PCB Debug 3 wk 3/1/06 Lab Test 1 month 3/31/06 Irradiation Tests GOL + SoS

  10. Why SoS • There is no guarantee that GOL can withstand ~10 times more radiation than what has been tested. • We do not know if more bandwidth would be needed. • We are designing a Link-on-Chip ASIC for the LAr upgrade. This chip may be used for the ID upgrade as well. • This project has just been started. Here I report on the first irradiation test and the actions we take based on the preliminary result. GOL + SoS

  11. The Irradiation of one SoS chip • A laser driver chip based on 0.5 m SoS technology was irradiated at MGH (230 MeV proton). • Total dose: 116 Mrad. • Error free at 1.5 krad/sec and up to 17 Mrad. LAr upgrade okay. • Observed current increase at very high dose rate. GOL + SoS

  12. The SoS test chip • In CMOS layout, the technique to combat the leakage current is the enclosed layout transistor (ELT) and the guard-ring around the transistors. In SoS, only ELT is needed. • We will use the new 0.25 m SoS technology for the LOC design. In order to probe the total dose limit, to check ELT on SoS, and to check layout parameters on design blocks like the PLL, we submitted a dedicated test chip mid October. • The test of this chip is in preparation (3 slides back) and the irradiation test is aimed for April 2006. GOL + SoS

  13. 4 Ring oscillators PLL parts 12 X 8 Transistor Array 5 Shift registers 6 Individual Gates The SoS test chip block diagram • 12X9 transistor array, ELT and “standard” layout, NMOS and PMOS with different size.Test layout techniques and rad-hard limit. • 4 ring oscillators (ELT, “std”, different transistor size). Test SEUs. • 5 shift Registers (… + various resistors, majority voting). Test SEUs. • 6 individual gates (ELT and “std”). • PLL parts: • Div16 • VCO • PFD Many parameters will be measured in lab and in irradiation. The results will guide us in designing of the LOC chip. GOL + SoS

  14. Majority vote circuitry Shift Registers CMOS Ring Oscillators Individual gates Differential Ring Oscillator Resistors PLL cells Transistors array The SoS test chip layout GOL + SoS

  15. Looking for E/O devices • We also started to look for laser diodes. We tested two surface emitting lasers. One long wavelength and can couple to single mode fiber, one VCSEL. The preliminary results are briefly reported here. GOL + SoS

  16. Test results on the GSE laser We exposed 12 Grating-outcoupled Surface-Emitting laser (1310 nm) up to 22.3 Mrad at IUCF with 200 MeV proton. The lasers that received 11.4 Mrad total dose still pass 2.5 Gbps eye mask test. 1.8 Mrad Pass. 5.9 Mrad Pass. 11.4 Mrad Pass. 22.3 Mrad Fail. GOL + SoS Group C Group D

  17. Test results of a 10 GHz VCSEL Preliminary test results on the ULM 10 GHz VCSEL: We irradiated 2 ULM 10 GHz VCSELs at MGH. The VCSEL were biased during irradiation. The total dose received is 116 Mrad. All DC parameters are still within spec after the irradiation. Eye diagram and other AC parameters will be measured soon. GOL + SoS

  18. Summary • The GOL test program has been started and is on track. • We designed and submitted a dedicated SoS test chip to check out layout techniques and measure related parameters. The lab and irradiation tests of this chip is in preparation. • We have tested the GSE lasers and find them useful in 11 Mrad environment. The GSE lasers can couple to single mode fibers. The results are accepted for publishing by Photonics Technology Letters (PLT). • We have identified a 10 GHz VCSLE and preliminary test results show potential in use with 100 Mrad. More tests are on going and more VCSELs will be tested. GOL + SoS

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