Dynamically Reconfigurable Architectures: An Overview

1. Dynamically Reconfigurable Architectures: An Overview Juanjo Noguera Dept. Computer Architecture (DAC-UPC) jnoguera@ac.upc.es

2. Outline • Introduction • Reconfigurable Computing • Reconfigurable devices and systems • Reconfigurable Systems Classification • Reconfiguration Methods • Reconfigurable Instruction Set Processors • ASIP-based approach • Coprocessor-based approach • Conclusions

3. Introduction • Reconfigurable Computing (RC) is an emerging paradigm for digital systems design • Technology improvements have made possible new programmable logic devices (FPGAs, CPLDs) • Objective of the talk: Give an overview of RC concepts and introduce the Reconfigurable Instruction Set Processors.

4.  Performance •  Power consumption •  Flexibility •  Programming  Specialization Introduction (II) • RC objectives: Specialization, performance, flexibility • Basic idea: “Programmable Hardware”

5. Performance Flexibility, Power Application SpecificSystems ReconfigurableComputing GPP RC DSP General Purpose Systems ASIC Cost Performance Introduction (III) • RC comparison versus other alternatives

6. Outline • Introduction • Reconfigurable Computing • Reconfigurable devices and systems • Reconfigurable Systems Classification • Reconfiguration Methods • Reconfigurable Instruction Set Processors • ASIP-based approach • Coprocessor-based approach • Conclusions

7. Logic Bloc I/O Bloc InterconnectionStructure Reconfigurable Devices • General device architecture Reconfigurable Computing

8. B B A A C C Continuous Routing Structured Routing Reconfigurable Devices (II) • Routing strategies Reconfigurable Computing

9. App 1 -> Bitstream 1 • App 2 -> Bitstream 2 • App n -> Bitstream n Reconfigurable Devices (III) • SRAM based devices with infinite number of reconfigurations Configuration Bitstream110011101 ... Reconfigurable Computing Reconfigurable Device

10. PLD PLD PLD PLD PLD PLD Reconfigurable Systems (I) • Rapid System (ASIC) Prototyping CPU PLD PLD PLD PLD Reconfigurable Computing

11. Reconfigurable Systems (II) Host Computer • Reconfigurable Systems Classification PLD (d) CPU Reconfigurable Computing (c) RAM PLD SYSTEM BUS PLD RAM I/O PLD (b) RAM (a)

12. Reconfiguration Methods (I) • Compile Time Reconfiguration (CTR) • Device configuration is fixed during application run time execution • Run Time Reconfiguration (RTR) • Device configuration changes during application run time execution • RTR strategies • Global RTR • Partial RTR Reconfigurable Computing

13. #2 Reconfiguration Reconfiguration #4 Execution Execution Reconfiguration Execution Reconfiguration Methods (II) • Global Run Time Reconfiguration (Single context) Application #1 #2 Reconfigurable Computing #3 #4 Reconfiguration Contexts #1 Dynamically Reconfigurable Device

14. #4 #1 Reconfiguration #2 Reconfiguration Methods (III) • Partial Run Time Reconfiguration (Multiple context) Aplicació #1 #2 Reconfigurable Computing #3 #4 #4 #1 Reconfiguration Contexts #3 Dynamically Reconfigurable Device

15. Reconfiguration Methods (IV) • Run-Time Reconfiguration Challenges • Temporal Partitioning • Context Scheduling (static) • Reconfiguration Latency Overhead • Configuration Pre-fetching • Configuration Caching • Configuration Compression Reconfigurable Computing

16. Outline • Introduction • Reconfigurable Computing • Reconfigurable devices and systems • Reconfigurable Systems Classification • Reconfiguration Methods • Reconfigurable Instruction Set Processors • ASIP-based approach • Coprocessor-based approach • Conclusions

17. Introduction • By including reconfigurability we can increase flexibility with high specialization Reconfigurable Instruction Set Processors Processor PLD Reconfigurable Processor

18. · · · · · · Task 1 Task K Task K+1 Task N Software Hardware · · · Software Hardware Task 1 Task 2 Task N Introduction (II) • Coprocessor based approach • ASIP based approach Reconfigurable Instruction Set Processors

19. Coprocessor based approach (I) • Typical example: CPU + PCI board • Altera ARC-PCI • Compaq Pamette • System on Chip (SoC) • Altera´s Excalibur device • Chameleon Systems, Inc. Reconfigurable Instruction Set Processors

20. Coprocessor based approach (II) • Altera ARC-PCI Reconfigurable Instruction Set Processors

21. Coprocessor based approach (III) • Compaq Pamette Reconfigurable Instruction Set Processors

22. Coprocessor based approach (IV) • Altera´s Excalibur device • Embedded Processor: ARM, MIPS or NIOS Reconfigurable Instruction Set Processors

23. Coprocessor based approach (V) • Chameleon Systems, Inc. Reconfigurable Instruction Set Processors

24. Fetch Decode Issue Integer Unit FP Unit Branch Unit LD/ST Unit Reconfigurable Unit ASIP based approach (I) • Reconfigurable unit within CPU Reconfigurable Instruction Set Processors

25. C Code Compiler Instruction Description (Configuration bits) Assembly Code ASIP based approach (II) • Challenge: CAD tools Reconfigurable Instruction Set Processors

26. C Code Compiler Structure C Parsing Optimizations Hardware Estimator Inst. Identification Inst. Selection Hardware Generation Config. Scheduling Code Generation Assembly Code Configuration bits ASIP based approach (III) Reconfigurable Instruction Set Processors

27. 32 32 32 32 32 32 5 5 4 5 Register File ALU MUX Encoded Instruction Word RFU ASIP based approach (II) • Example: Philips CinCISe Architecture Reconfigurable Instruction Set Processors

28. 27 26 25 23 22 30 27 26 25 22 XOR 7 6 5 4 3 2 ASIP based approach (III) • Application example: DES & A5 encryptation algorithms Reconfigurable Instruction Set Processors srl $13, $2, 20 andi $25, $13, 1 srl $14, $2, 21 andi $24, $14, 6 or $15, $25, $24 srl $13, $2, 22 andi $14, $13, 56 or $25, $15, $14 sll $24, $25, 2 srl $24, $5, 18 srl $25, $5, 17 xor $8, $24, $25 srl $9, $5, 16 xor $10, $8, $9 srl $11, $5, 13 xor $12, $10, $11 andi $13, $12, 1

29. Conclusions • Reconfigurable Computing is an emerging and interesting computing paradigm • RC devices and architectures are becoming a reality • There is a big challenge is High-level synthesis (CAD) tools

30. ?? RC DSP ASIC Conclusions (II) Flexibility, Power • What is the future ?? RC GPP RC Performance