Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs)

1. Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [2Gbps Transmission Demonstration using p/2 DBPSK Alternative] Date Submitted: [17 September, 2007] Source: [Y. Katayama, A. V-.Garcia, D. Nakano, T. Beukema] Company [IBM] Address [1623-14 Shimotsuruma Yamato Kanagawa 242-8502 Japan] Voice:[+81.46.215.4879], E-Mail: [yasunaok@jp.ibm.com ] Re: [] Abstract: [Present an alternative way of generating p/2 DBPSKcommon waveform with its 2Gbps data rate demonstration] Purpose: [Discussion purpose only ] Notice: This document has been prepared to assist the IEEE P802.15. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P802.15.

2. 2Gbps Transmission Demonstration using p/2 (D)BPSK Alternative Y. Katayama, A. V.-Garcia*, D. Nakano, and T. Beukema*IBM Research, Tokyo Research Laboratory*IBM T. J. Watson Research Center

3. Q Q I I Q QPSK QFSK I p/2-shift (D)BPSK Modulation Formats Discussed in IEEE 802.15.3c FM discriminatorDifferential detectionCoherent detection … OOK Common Waveform p/2 shift Q OQPSK HW demonstrated by IBM Filter I Q BPSK(Bipolar ASK) p/4 rotate With or w/o (1+x2) precoding MSK/GMSK Filter 8PSK16QAM OFDM

4. Summary of Link Experiments • All used +7 dBi gain planar folded dipole antenna on PCBs. • All used ≈ +10 dBm transmit power.

5. Clock inputs for MSK. No clock inputs for QFSK QFSK/MSK Demo System TX Baseband(FPGA board) Camera HD-SDI1.485Gbps 60GHz TX RF module I modulation Packetizer ECC encode DVI PC Q 2Gbps RX baseband(FPGA board) 1080i HDTV monitor 60GHz RX RF module DVI Depacketizer Demodulation ECC decode Video output FM discriminator

6. TX Baseband Block Diagram FPGA board Differential 1.485Gbps To RF module Rocket I/O Interface 20bit 10bit x2 10bit x2 10bit x2 10bit x2 20bit I Rocket I/O Interface CDR HD-SDI Framer Async FIFO Packetizer FEC Encoder QFSK Modulator Scrambler Rocket I/O Interface Q Differential 1Gbps x2 Clock buffer Recovered Clock 75MHz 100MHz

7. RX Baseband Block Diagram FPGA board From RF module 10bit x2 10bit x2 10bit x2 10bit x2 20bit 20bit Rocket I/O Interface CDR FEC Decoder Video converter HD-SDI Interface Async FIFO Framer Descrambler Differential 2Gbps Clock buffer Recovered Clock 125MHz* DCM 75MHz 75MHz 100MHz

8. Error Pattern Measurements (w/o FEC) • Under multi-path environment (ordinary lab) • Packet loss is dominant (white horizontal lines) • Burst errors • Header detection failure • Packet recovery is effective • Under multi-path suppressed environment (radio anechoic room) • Random error is dominant (white dots) • Random error correction is effective • RS(255,239) is not effective unless appropriately interleaved • But difficult with FPGA implementation then Demo/Test setup in radio anechoic room Packet loss dominant (Phase I) Random error dominant (Phase II)

9. FPGA Board Functional Diagram Aux. Aurora/Infiniband for Scalability Data Input Data Output 4 HD-SDI HD-SDI Motion Co-Processor De-interlacer Xilinx Vertex-II Pro XC2VP50 DVI DVI Re-Configurable System Logicwith 2x powerPC I/O I/O 4 CameraLink Aurora/Infiniband 224MBSDRAM total I/O Controllers CompactFlash Mouse(PS2)Trackball RS232(Camera) Aux. RS232 IEEE 1394a Keyboard USB

10. … … … … … … Proprietary Wireless Frame Format Baseband input format (1.485 Gbps, HD-SDI 1080i) 44000 b / line Serial SAV Line No. CRCC AUX (Audio, etc.) Effective Line (YCbCr 4:2:2) EAV 300-b Packet 80 b 38400 b 40 b 40 b 5360 b 80 b Baseband output format (2 Gbps, parity/other overheads added) 10 b @ 75 MHz 10 b @ 100 MHz BCH(350,300) I Serial BCH Parity Q 10 b @ 75 MHz 10 b @ 100 MHz POB Parity POB(150,149;3) Subframe(25+25 packets) H0 H1 H2

11. FEC Encoder/Decoder Design FPGA (Xilinx Vertex II Pro) implementation result • Encoder • One clock latency • Decoder • Inner: BCH(350,300) on GF(210) • Stateless (oneshot) coef. gen. • Outer: POB(150,149;3)on GF(210) • Stateless and shared coef. gen. • Syndrome recalc. • Buffer size remains comparable to original block code. 20b@100MHz = 2Gbps 20b 20b 20b 20b

12. Conclusion • Demonstrated 2Gbps transmission • SiGe radio with FM discriminator • QFSK modulation • Proprietary frame/FEC (for FPGA implementation) • Pointed out that QFSK is an alternative way of generating p/2 (D)BPSK waveform • Verified with HW @ 2Gbps • Radio supports the necessary BW • Demo running at both IBM T. J. Watson Research Center and Tokyo Research Laboratory