Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems

1. Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems Marcus T. Schmitz and Bashir M. Al-Hashimi University of Southampton, United Kingdom Petru Eles Linköping University, Sweden

2. Contents • Motivation & Introduction • Dynamic Voltage Scaling • Co-Synthesis with DVS Consideration • DVS optimised Scheduling • DVS optimised Mapping • Experimental Results • Conclusions

3. Motivation Low Energy: • Portable Applications • Autonomous Systems • Feasibilty Issues (SoC - heat) • Operational Cost and Environmental Reasons • System Level Co-Design: • Shrinking Time-To-Market Windows • Reducing Production Cost • High Degree of Optimisation Freedom

4. Introduction Dynamic Voltage Scaling System Level Co-Synthesis Energy-Efficient Co-Synthesis for DVS Sytems

5. Dynamic Voltage Scaling (DVS) Energy vs. Speed 1.2 DVS Processor 1 Frequency 0.8 VR f Reg. Energy 0.6 Voltage/Frequency 0.4 0.2 0 1 1.5 2 2.5 3 3.5 4 4.5 5 1/Speed Available from: Transmeta, AMD, Intel

6. Co-Synthesis for DVS Systems System Specification, Technology Lib. Allocation Mapping Scheduling Designer driven EE-GMA Voltage Scaling EE-GLSA Evaluation

7. Voltage Scaling DVS in Distributed Systems [23] Input: Scheduling (mapping) Power profile Output: scaled voltage for each DVS task Emax Esc < Emax P P Slack PE0 PE0 CL0 CL0 2.3V 3.3V 2.4V PE1 PE1 d t d t @ Vmax @ dyn. V

8. Energy-Efficient Scheduling • Two objectives: • Timing feasibility • Garantee deadlines • Low energy dissipation • Optimisation DVS usability – Slack time Traditional scheduling technique focus mainly on timing feasibility! • Problem due to power variations: • Simply increase deadline slack leads to sub-optimal solutions!

9. Energy-Efficient Scheduling S1: E=71J E=65.6J P P PE0 t t t t 5 4 5 4 Slack  Savings  DVS PE1 t t t t 1 1 2 2 t t 0 0 PE2 Slack t 3 t 6 t t 3 6 t t S2: E=71J E=53.9J P P Slack Slack  Savings  PE0 t t 5 4 t t 4 5 DVS PE1 t t t t 1 1 2 2 t t 0 0 PE2 t t 3 3 t t 6 6 t t

10. t1 t0 t4 t3 t2 List Scheduler t0 t1 t2 t3 t4 Energy-Efficient Scheduling • Based on Genetic List Scheduling Algorithm [6,10] • Task priorities are encoded into priorities strings Schedule • Duties of the Scheduler: • Select ready task with highest priority • Schedule selected task • Update schedule and ready list • Repeat until no un-scheduled task is left PS

11. List Scheduler Assign fitness DVS Insertion Rank individuals Selection Mating Mutation EE-GLSA No Hole Filling! No Mapping! Initial Population Timing, Energy Optimised Population high low GA

12. Advantages • Optimisation can be based on an arbitrary complex fitness function, including: • Timing • Energy (DVS technique) • Enlarged search space (|T+C|! different schedules) • Trade-off freedom: Synthesis time <-> quality • Easily adaptable to computing clusters • Multiple populations with immigration scheme

13. Hole filling d3 d4 d2 Hole Filling Problem t0 PE0 t4 t2 7 t3 t3 1 d2 d3,4 t1 4 t4 6 t2 4 PE1 t0 t1 Therefore, priorities decide solely upon execution order!

14. d2 d1 LS Task Mapping • Why seperation from the list scheduling? • Regardless of priorties, greedy mapping P t0 7 PE0 t1 4 PE1 t t2 d1,2 5

15. d2 d1 LS Task Mapping • Make greedy mapping decision based on: • Timing • Energy P t0 7 PE0 ? t1 4 PE1 ? t t2 d1,2 5

16. d2 d1 LS Task Mapping • Make mapping decision based on: • Timing • Energy P t0 7 PE0 t0 t1 4 PE1 t t2 d1,2 5

17. d2 d1 LS Task Mapping • Make mapping decision based on: • Timing • Energy P t0 7 PE0 t0 ? t1 4 PE1 ? t t2 d1,2 5

18. d2 d1 LS Task Mapping • Make mapping decision based on: • Timing • Energy P t0 7 PE0 t0 t1 4 PE1 t2 t t2 d1,2 5

19. d2 d1 LS Task Mapping • Make mapping decision based on: • Timing • Energy P t0 7 PE0 t0 t1 4 PE1 t2 t t2 d1,2 5

20. d2 d1 LS Task Mapping • Make mapping decision based on: • Timing • Energy P t0 7 PE0 t0 t1 4 PE1 t2 t1 t t2 d1,2 5

21. d2 d1 LS Task Mapping • Make mapping decision based on: • Timing • Energy P t0 7 PE0 t0 t2 t1 4 PE1 t1 t t2 d1,2 5

22. CPU DVS-CPU 0 0 1 1 2 3 4 2 5 d 6 ASIC d Genetic Mapping Algorithm [8] Task mapping are encoded into mapping strings Chromosome

23. Assign fitness Insertion Rank individuals Selection Mating Mutation EE-GMA Including DVS EE-GLSA Initial Population Timing, Energy + Area Optimised Population high low GA

24. Experimental Results • 4 Benchmark Sets: • 27 generated by TGFF [7] • 8 to 100 tasks: Power variations 2.6 • 2 Hou examples taken from [13] • 8 to 20 tasks: Power variations 11 • TG1 and TG2 taken from [11] • 60 examples with 30 tasks, each: No power variations • Measurement application taken from [3] • 12 tasks: No power profile is provided • Power and time overhead for DVS is neglected • Average results of 5 optimisation runs

25. Schedule Optimisation

26. Schedule Optimisation

27. Mapping Optimisation

28. Conclusions • DVS capability can achieve high energy savings in distributed embedded systems • Proposed a new energy-efficient two-step mapping and scheduling approach • Iterative improvement provides high savings / ad hoc constructive techniques are not suitable • Optimisation times are reasonable • Additional objectives can be easily included • Consideration of power profile information leads to further energy reductions