Nuclear Physics Group Meeting Version-2 Latch Card Testing

1. Nuclear Physics Group MeetingVersion-2 Latch Card Testing 2011/01/12 Jia-Ye Chen

2. Content • Latch Card Version 2 • Control and Status Register 2 • Trigger/Busy • Testing Signal • Testing Results • Further Testing

3. Latch Card Version 2 • Edge Trigger Mode • Internal Clock : 125 MHz (8 ns) • 2nd Control and Status Register • CSR2 (default : 0x000000c0) • FIFO status register = 01 (default = 00) Trigger Busy

4. Control and Status Register 2 (CSR2) • Adjustable Delay • 64 clocks * 8 ns = 512 ns • Delay=0, earliest signal (default) • Delay=3f, edge signal • 6-clock OR operation window latchORoperation(iOR,iDelay);

5. Trigger/Busy Trigger Busy Jittering (Two 33MHz Readout Internal Clocks)

6. Testing Signal signal latch trigger sis3610 trigger latch busy

7. OR-window and Delay Test (I) • Input Data Pattern (0x ff7f fffefeff 7fff) • 5-event FIFO Readout is exactly identical. • First 6-clock window output as the fine scanning boundary. latchRunTest(id,runs); id : latch card id runs : number of iteration

8. OR-window and Delay Test (II) Delay Box = 192 ns Delay Box = 128 ns

9. OR-window and Delay Test (III) Delay Box = 128 ns Scan 100 times Delay Box = 64 ns

10. CODA Readout (14 hours)

11. Further Testing • Non-uniform data pattern input testing.