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Technion - Israel institute of technology department of Electrical Engineering. הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל. High Speed Digital Systems Laboratory. המעבדה למערכות ספרתיות מהירות. ARMOR A synchronous R ISC M icroprocess or. Performed by: Tziki Oz-Sinay, Ori Lempel
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Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High Speed Digital Systems Laboratory המעבדה למערכות ספרתיות מהירות ARMORAsynchronous RISC Microprocessor Performed by: Tziki Oz-Sinay, Ori Lempel Instructor: Rony Mitleman סמסטרים חורף וקיץ תשס"ד 1
High Speed Digital Systems Laboratory המעבדה למערכות ספרתיות מהירות Abstract The benefits of asynchronous VLSI circuit design include: elimination of clock skew problems, average-case performance, adaptivity to processing and environmental variations, lower system power requirements and reduced noise. The ARMOR is an asynchronous RISC microprocessor with an out-of-order execution engine. It is designed using the Balsa asynchronous hardware description language and environment tools. The synthesized ARMOR core may then be implemented on the Xilinx VertexPro FPGA and interface with synchronous memory modules. 2
Xilinx VertexPro Data Cache Inst Cache SDRAM 64KB SDRAM 64KB ARMOR core Watch Window (debug) Program Code (assembler) PCI Interface High Speed Digital Systems Laboratory המעבדה למערכות ספרתיות מהירות SystemDescription 3
Out Of Order Engine BranchDecision Op[3:0] ALU0PDst[4:0] PDst[4:0] ALU0Res[15:0] SrcVal1[15:0] ALU1PDst[4:0] Op[3:0] SrcVal2[15:0] ALU1Res[15:0] LDst[2:0] LDst[3:0] Imm[15:0] Inst[15:0] Instruction Fetch Execute Val15:0] Retire Decode LSrc[3:0] Rename Write Back Op[3:0] DataIn[15:0] Imm[15:0] PDst[4:0] MemPDst[4:0] PDst[4:0] Mem Access SrcVal1[15:0] DataOut[15:0] Addr[15:0] SrcVal2[15:0] ReadWrite# Imm[15:0] PC[15:0] Inst[15:0] Addr[15:0] DataIn[15:0] DataOut[15:0] SYNCHRONIZATION SDRAM SDRAM High Speed Digital Systems Laboratory המעבדה למערכות ספרתיות מהירות ARMOR Pipeline 5
branches non-mem inst mem inst non-branch inst BranchDecision to IFU DATA CACHE ALU0 ALU1 RS0 RS1 Inst from ID ROB RAT RRF In Order Out of Order High Speed Digital Systems Laboratory המעבדה למערכות ספרתיות מהירות ARMOR Out-Of-Order Engine 5
