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EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrow’s Technology Today

EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrow’s Technology Today. 80486 and Pentium. 80486 Microprocessor Family. 80486 Microprocessor Introduced in 1989 High Integration On-chip 8K Code and Data cache Floating Point Unit Paged, Virtual Memory Management

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EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrow’s Technology Today

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  1. EZ-COURSEWAREState-of-the-Art Teaching ToolsFrom AMSTeaching Tomorrow’s Technology Today www.advancedmsinc.com

  2. www.advancedmsinc.com

  3. 80486 and Pentium www.advancedmsinc.com

  4. 80486 Microprocessor Family • 80486 Microprocessor • Introduced in 1989 • High Integration • On-chip 8K Code and Data cache • Floating Point Unit • Paged, Virtual Memory Management • 168-pin PGA package • Multiprocessor Support • Multiprocessor Instructions • Cache Consistency Protocols www.advancedmsinc.com

  5. Internal Architecture of the 80486 • Complex Reduced-Instruction-Set Computer (CRISC) • RISC integer core www.advancedmsinc.com

  6. Real-Mode Software Model • the same as that shown for the 80386 www.advancedmsinc.com

  7. Protected-Mode Software Architecture AC: Alignment-Check flag When this bit is set, an alignment check is performed during all memory accesses at privilege level 3. If an unaligned access takes place, exception 17 occurs. www.advancedmsinc.com

  8. Control Registers • AM : alignment mask -- If this is switched to 0, the alignment check is masked out. • NE : Numeric Error • CD : cache disable • NW : not write-through • WP : write protect • PCD : page-level cache disable • PWT : page-level write transparent www.advancedmsinc.com

  9. System-Control Instruction Set + a flush bus cycle + a write-back bus cycle www.advancedmsinc.com

  10. Page Directory and Page Table Entries www.advancedmsinc.com

  11. Hardware Architecture of the 80486 www.advancedmsinc.com

  12. Signal Interfaces Pseudo-lock www.advancedmsinc.com

  13. On-Chip Cache of the 80486SX www.advancedmsinc.com

  14. Pentium Processor • Pentium Processor • 32-bit Microprocessor • 32-bit addressing • 64-bit Data Bus • Superscalar architecture • Two pipelined integer units • Capable of under one clock per instruction • Pipelined Floating Point Unit • Separate Code and Data Caches • 8K Code, 8K Write Back Data • 2-way 32-byte line size • MESI cache consistency protocol • Advance Design Features • Branch Prediction • 237-pin PGA www.advancedmsinc.com

  15. Internal Architecture of the Pentium Processors www.advancedmsinc.com

  16. I1 I3 I5 I7 PF I2 I4 I6 I8 I1 I3 I5 I7 D1 I2 I4 I6 I8 PF I1 I2 I3 I4 I1 I3 I5 I7 D2 I2 I4 I6 I8 D1 I1 I2 I3 I4 I1 I3 I5 I7 D2 I1 I2 I3 I4 EX I2 I4 I6 I8 I1 I2 I3 I4 I1 I3 I5 I7 EX WB I2 I4 I6 I8 I1 I2 I3 I4 WB Pentium Processor • Pipeline and Instruction Flow • 5 stage pipeline PF : prefetch D1 : Instruction decode D2 : Address Generation EX : Execute -ALU and Cache Access WB : Write Back Intel 486 Pentium www.advancedmsinc.com

  17. Pentium Processor • “U”, “V” pipes - “pairing” • U : any instruction • V : ‘simple instructions” as defined in the ‘Pairing” rules PF : instructions on chip cache or memory -> prefetch buffers prefetch buffers - two independent pairs of line size(32 bytes) D1 : two parallel decoders D2 : address generation for operand fetch EX : ALU operations and data cache access WB : modify processor state ; complete execution www.advancedmsinc.com

  18. Branch Prediction • Branch Prediction • Branch Target Buffer • The processor accesses the BTB with the address of the instruction in the D1 stage example) inner_loop : mov byte ptr flag[edx], al PF D1 D2 EX WB add edx, ecx PF D1 D2 EX WB cmp edx, FALSE PF D1 D2 EX WB jle inner_loopPF • 486 : 6 clocks Pentium : 2 clocks with branch prediction www.advancedmsinc.com

  19. EFLAGS www.advancedmsinc.com

  20. Control Registers of the Pentium Processor www.advancedmsinc.com

  21. Enhancements to the Instruction Set www.advancedmsinc.com

  22. Hardware Architecture www.advancedmsinc.com

  23. Memory Subsystem www.advancedmsinc.com

  24. Organization of the DRAM Array www.advancedmsinc.com

  25. RAS/CAS address MUX www.advancedmsinc.com

  26. Data Bus Transceiver Circuitry www.advancedmsinc.com

  27. On-Chip Cache www.advancedmsinc.com

  28. On-chip cache operating mode www.advancedmsinc.com

  29. www.advancedmsinc.com

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