Design of Packet-Fair Queuing Schedulers Using a RAM-Based Searching Engine

1. Design of Packet-Fair Queuing SchedulersUsing a RAM-Based Searching Engine IEEE JSAC, Vol.17, No 6, June 1999 H. Jonathan Chao 외 이 융 yiyung@mmlab.snu.ac.kr

2. Contents • PFQ • 기존 연구 및 일반적인 구현 기법 • General Shaper-Scheduler • Slotted Updates • Implementation Architecture • Time-Stamp Aging Problem • Conclusion

3. PFQ(Packet Fair Queuing) • PFQ 알고리즘의 전개 방향 • GPS(General Processor Sharing) • WFQ(PGPS) • GPS보다 Lmax이상 뒤쳐지지 않는다. • SCFQ, STFQ : Implementation Cost의 decrease • WF2Q : WFQ의 단점 보완. • GPS에 가장 가까운 모델. • WFI Metric 이용 • S(t) < = V(t) check • GPS 보다 WF2Q는 한 패킷 이상 앞서지 않는다는 점까지 추가 • WF2Q+ • WF2Q의 Implementation Cost의 decrease • 본 논문의 주요 고려 대상

4. Time Computation(1/2) Virtual Start Time Virtual Finish Time Virtual Time Implementation of PGPS Where : interval( )에 busy인session 집합 : weight for session i

5. Time Computation(2/2) • WF2Q+ • WF2Q • emulates the progress of GPS system • WF2Q+ • be computed directly from the packet system

6. Packet Scheduler Packet Scheduler Data Memory Packets Packets Packet in Packet out Write/read Address Packetheader Packet Scheduler CPU PacketSearch Engine

7. PFQ • 기존 연구 및 일반적인 구현 기법 • General Shaper-Scheduler • Slotted Updates • Implementation Architecture • Time-Stamp Aging Problem • Conclusion

8. Existing Implementation Researches • PFQ’s Implementation depends on • system virtual time computation • relative ordering via finish time in a priority queue • Efficient hardware-based priority queue • binary tree of comparators • sequencer chip(ASIC) • Search-Based version • This paper • new ASIC(PCAM : priority content addressable memory) • Author • off-chip memory, hierarchical searching • RSE(RAM-based Search Engine) • commercial memory and FPGA chips

9. V(t) StartTime A B Conceptual Framework(1/2) • W = max {start time} • N : Total number of sessions in the system

10. Conceptual Framework(2/2) Logical queue per session • Head-pointer memory : 각 Queue의 Header pointer 저장 • Tail-pointer memory : 각 Queue의 Tail pointer 저장 • Idle queue : Data memory의 Idle space 유지

11. Design Issue-I(1/3) • Scheduler Queue • Search-based approach Vs. Sorting-based approach Data Structure Implementation of a scheduler queue using the RSE

12. Design Issue-I(2/3) • Hierarchical searching with a tree structure • Data structure : Tree of priority encoders & decoders 0 1 0 0 1 1 0 0 0 0 0 1 1 0 0 1 2 3 4 5 6 7 5 1 0 1

13. 1 1 0 1 0 1 5 Design Issue-I(3/3) • Output of the m-bit time stamp F in hierarchical searching(L=3)

14. Design Issue-II • Shaper Queue • Eligibility Test : S(t) <= V(t) • V(t)-> col addr and compare • move eligible packets to scheduler queue F V(t) S

15. Time-stamp Overflow Control • Time-stamp overflow • Maximum value of F : M-1 • maximum packet length over minimum allocated BW : • F: 단조 증가, 한계치(M-1)에 도달 -> Overflow • CZ(Current zone bit) • 현재 Service되는 Packet Zone을 가리킴

16. Time-stamp Overflow Control • MSB of F does not change more than once when serving in the current zone -> packet out-of-sequence(x)

17. PFQ • 기존 연구 및 일반적인 구현 기법 • General Shaper-Scheduler • Slotted Updates • Implementation Architecture • Time-Stamp Aging Problem • Conclusion

18. Slotted Updates(1/2) • Scheme • Variable sized packet -> fixed-length segments • Packet Scheduler : slotted(synchronous) system • T : one slot time -> W(t,t+d) = dT : normalized to one • All times(start, finish, system time) -> integer • Ex) -> next page • Discussion • Incomplete segment • underutilized, non-workconserving. • limited by one time slot. • Inaccuracy <- discrete time event(arrival, departure)

19. Slotted Updates(2/2)

20. Advantage using Slotted Update • 일반적인 Shaper Queue • Maximum N packets are moved to Scheduler Queue • Fixed Segment Using Slotted Update • Researches about ATM cells • Same effect as ATM cell(fixed size) • V(t)(=a)의 값을 가지고 column search • only two packets at most need to be transmitted to the scheduler queue • packet with the smallest finish time in column a • packet with the smallest finish time in column b(b는 현재 전송되고 있거나 막 전송한 패킷의 start time)

21. Implementation Architecture

22. Basic Operations • At every time slot, CPU( using Smin(start time queue)) -> virtual time update(=a) • Shaper Queue • new HOL packet : 이전 패킷의 finish time -> CPU • start time, finish time 계산 -> Shaper Queue • Scheduler Queue • packet(k) selection(minimum finish time) -> 전송 • Fk is stored in the finish time queue( start time : b ) • a 와 b는 2-D RSE에서 eligibility test를 위해서 사용됨

23. 2-D RSE • W groups at level 0 to index a column

24. Time-Stamp Overflow(1/2) • F and S’s overflow • F = S + D • F is bounded by max packet length and min alloc bw • overflow information : 2 bit F < S F < S F > S F > S

25. Time-Stamp Aging Problem(1/2) • Finish time은 다음 패킷의 start time계산을 위해서 값이 저장 • Virtual system time도 overflow할 수 있다. • 그 때, finish time은 obsolete • V(t)는 한번에 W-1까지 증가할 수 있다. • Purging Algorithm • check each entry and purge all obsolete ones(should be fast) • perform many purging operations in a time slot(difficult) • Solution • V(t) can overflow at most once in every time slot • have to see multiple time slot -> Periodic purging scheme

26. Time-Stamp Aging Problem(2/2) • Check A entries in T time slots • A >= N-1 -> 2A memory accesses • 2T memory accesses(read/wrtie) • T x slot time >= (2T +2A) x memory cycle • EX) • 64byte packet segment. 10Gbit(51.2ns) • memory cycle 10ns, N = 32K • A = N = 32768 -> T = 21006, A/T = 1.56 purging operations • Cv(t) : multibit counter, Time Zone Indicator for V(t) • Oi : obsolete bit counter • Ci : Time Zone Indicator for Fi

27. Flow chart of purging scheme

28. Conclusion • A novel RSE for PFQ • hierarchical searching • commercial memory chip, independent of # of session • 2-D RSE for general shaper-scheduler • at most two packets to be transferred • Time-Stamp overflow • 2bit zone bit • Time-Stamp Aging Problem • V(t)’s overflow • multibit counter variable within a fixed period